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| 型號(hào)： | 21084 |
| 英文描述： | AMD-K6 Processor Bios Design Application Note AMD-K6 Processor I/O Model Application Note |
| 中文描述： | 的AMD - K6處理器的BIOS設(shè)計(jì)中的應(yīng)用注意的AMD - K6處理器的I / O模型的應(yīng)用說(shuō)明 |
| 文件頁(yè)數(shù)： | 7/14頁(yè) |
| 文件大?。?/td> | 357K |
| 代理商： | 21084 |
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IBIS Modeling
3
21084D/0—June 1999
AMD-K6
Processor I/O Model
Figure 1. Modeling Example of Typical PCB Net
After the simulator has loaded the net input file, the simulator
can be instructed to generate a rising or falling transition at the
driver input to the processor driver (point ‘A’ in Figure 1). This
signal generator is represented in Figure 1 by the voltage
source input to the processor driver.
Setup and Hold Times
For each signal transition, the simulator can determine the
signal propagation delay from point ‘A’ to point ‘B’ under
worst-case, typical, and best-case conditions. The propagation
delay under worst-case conditions is used to determine if the
setup time at the destination receiver is met. Likewise, the
progagation delay under best-case conditions is used to
determine if the hold time at the destination receiver is met.
Figure 2 illustrates the timings that must be considered when
determining whether the setup time of a signal is met. The
timings are defined as follows:
I
T
period
is the period of the system clock
T
skew
is the maximum clock skew between the clock that
launches a signal (solid-line clock) and the clock that
captures a signal (dashed-line clock)
T
jitter
allowance between successive periods of the system clock
T
validmax
is the maximum valid delay of a signal from its
source
I
I
I
+
–
V
CC
R
1
R
2
A
B
AMD-K6
Processor
System Logic
PCB Trace
Driver
Receiver
Z
o
Voltage
Source
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