參數(shù)資料
型號(hào): 21084
英文描述: AMD-K6 Processor Bios Design Application Note AMD-K6 Processor I/O Model Application Note
中文描述: 的AMD - K6處理器的BIOS設(shè)計(jì)中的應(yīng)用注意的AMD - K6處理器的I / O模型的應(yīng)用說(shuō)明
文件頁(yè)數(shù): 10/14頁(yè)
文件大?。?/td> 357K
代理商: 21084
6
IBIS Modeling
AMD-K6
Processor I/O Model
21084D/0—June 1999
To ensure the hold time of a signal is met, the following
relationship must be met:
T
validmin
+ T
propmin
– T
skew
– T
jitter
> T
holdmin
Signal Quality
In addition to providing propagation delays, the simulator can
graphically display the output waveform presented at the
output of the driver and the corresponding waveform produced
at point ‘B’ in Figure 1. This display allows a designer to
determine if the signal quality at the destination is acceptable.
In addition to providing graphical data, most simulators
generate numerical data that quantifies various signal quality
characteristics.
The following list shows the signal quality characteristics that
typically concern designers (all measurements are taken at the
destination receiver):
I
Overshoot
—The difference between the maximum value of
the voltage of a rising signal and the nominal I/O V
CC
voltage (See Figure 4). Overshoot can adversely affect the
reliability of the destination receiver. The time during which
a signal remains above the nominal I/O V
CC
voltage is also a
reliability factor.
Undershoot
—The difference between the minimum value of
the voltage of a falling signal and ground (See Figure 5). As
with overshoot, undershoot can adversely affect the
reliability of the destination receiver.
Ringback
—In the case of a rising waveform, the difference
between the nominal I/O V
CC
voltage and the minimum
voltage of a signal after that signal has reached its maximum
value. In the case of a falling waveform, ringback is the
difference between the maximum voltage of a signal after
that signal has reached its minimum value and ground (See
Figures 4 and 5). Excessive ringing can cause the destination
receiver to falsely switch if the signal traverses the switching
threshold of the receiver.
Ring Settling Time
—In the case of a rising waveform, the
time between when a signal crosses one-half of the nominal
V
CC
I/O voltage and when the signal settles within the
specified tolerance of the I/O V
CC
voltage. In the case of a
falling waveform, ring settling time is the time between
when a signal crosses one-half of the nominal I/O V
CC
voltage and when the signal settles within a specific
I
I
I
相關(guān)PDF資料
PDF描述
21085 AMD-K6 Processor I/O Model Application Note AMD-K6 Processor Thermal Solution Design Application Note
21086 SYSCALL and SYSRET Instruction Specification? 341KB (PDF)
2108I ALARMMODUL
210A200 Synchro/Resolver Reference Oscillator
210A200B Synchro/Resolver Reference Oscillator
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