參數(shù)資料
型號(hào)： ZR36015PQC-30
廠商： Electronic Theatre Controls, Inc.
元件分類： 圓形連接器
英文描述： Circular Connector; No. of Contacts:10; Series:; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:12; Circular Contact Gender:Pin; Circular Shell Style:Cable Receptacle; Insert Arrangement:12-10
中文描述： 光柵座轉(zhuǎn)爐
文件頁(yè)數(shù)： 7/27頁(yè)
文件大?。?/td> 164K
代理商： ZR36015PQC-30
ZR36015
7
PRELIMINARY
The data seen on the Pixel Bus during Compressoin is shown in
Figure 5.
PIXEL PROCESSING TIMING
The leading edge of the frame is identified by the fall of VEN
(after the GO bit is set). Tge VDelay is counted from the follow-
ing rise of the VEN input. The HDelay is counted from the rise of
the HEN input. The HEN and VEN signals must remain high at
least until the end of the active image area (as defined by the
Configuration Register table).
HEN must conform to either A or B in Figure 8.
Within the image area defined by the VEN and HEN signals, is
the “Active Image Area”, which is determined by the HDelay,
HWidth, VDelay, and VWidth values in the configuration table.
Pixel processing is performed only on those pixels which lie in
the active image area defined in Figure 4. The width and height
of the active image area are determined by the “HWidth” and
“VHeight” values in the configuration register table.
If VWidth is set to zero (a special case), then lines will continue
to be processed for as long as VEN remains high (maximum of
8K lines). This feature allows processing of frames with an
1. The sync clock freq. of the coder bus side is SYSCLK in all modes.
Table 4: PXDATA Bus Sync Clock Frequency
MOD (1:0)
Pixel Side
Format
Coder Side
Format
PXDATA Bus Sync
Clock Freq.
1
0 (00)
(1:0:0)
(1:0:0)
SYSCLK
1 (01)
(4:2:2)
(4:2:2)
SYSCLK
÷
2
2 (10)
(4:2:2)
(4:1:1)
SYSCLK
÷
2
3 (11)
(4:1:1)
(4:1:1)
SYSCLK
÷
2
SYSCLK
HEN
MOD[1:0] = 0
PXDATA (15:8)
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Y9
Y10
Y11
Y12
Y13
Y14
MOD[1:0] = 1, 2
PXDATA (15:8)
Y1
Y2
Y3
Y4
Y5
Y6
Y7
PXDATA (7:0)
U1
V1
U2
V2
U3
V3
U4
MOD[1:0] = 3
PXDATA (15:8)
Y1
Y2
Y3
Y4
Y5
Y6
Y7
PXDATA (7:6)
U11
U12
U13
U14
U21
U22
U23
PXDATA (5:4)
V11
V12
V13
V14
V21
V22
V23
Figure 5. Functional Timing Chart - Pixel Bus Side
CLKCSC
CLKCSC
CLKCSC
unknown number of lines. At the end of processing, the “Number
of Lines” register will contain the number of lines that have been
processed. Figure 7 illustrates the “active image area” for this
special case.
Active Image
Area
EOS Output
HEN
V
Figure 6. Pixel Processing Image Area
B
Active Image
Area
EOS Output
HEN
V
Figure 7. EOS Asertion
N
相關(guān)PDF資料
PDF描述
ZR36016 INTEGRATED COLOR SPACE / RASTER-TO-BLOCK CONVERTER
ZR36016PQC-30 INTEGRATED COLOR SPACE / RASTER-TO-BLOCK CONVERTER
ZR36016 JPEG Pre- and Post-Processor(JPEG 先-后處理器)
ZR36050 JPEG Image Compression Processor(JPEG 圖象壓縮處理器)
ZR36060 Integrated JPEG Codec(集成JPEG編解碼器)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ZR36016 制造商:未知廠家 制造商全稱:未知廠家 功能描述:INTEGRATED COLOR SPACE / RASTER-TO-BLOCK CONVERTER
ZR36016PQC 制造商:ZORAN 功能描述:
ZR36016PQC-30 制造商:未知廠家 制造商全稱:未知廠家 功能描述:INTEGRATED COLOR SPACE / RASTER-TO-BLOCK CONVERTER
ZR36050 制造商:未知廠家 制造商全稱:未知廠家 功能描述:JPEG IMAGE COMPRESSION PROCESSOR
ZR36050PQC-21 制造商:ZORAN 功能描述:
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