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參數(shù)資料
| 型號： | ZR36015PQC-30 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 元件分類： | 圓形連接器 |
| 英文描述： | Circular Connector; No. of Contacts:10; Series:; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:12; Circular Contact Gender:Pin; Circular Shell Style:Cable Receptacle; Insert Arrangement:12-10 |
| 中文描述： | 光柵座轉(zhuǎn)爐 |
| 文件頁數(shù)： | 2/27頁 |
| 文件大?。?/td> | 164K |
| 代理商： | ZR36015PQC-30 |
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ZR36015
2
PRELIMINARY
SIGNAL DESCRIPTION
1. I = Input, O = Output, B = Bidirectional, Z = High Impedance.
Name
Type
1
Function
PXDATA(15:0)
B
Pixel side data bus. Input for compression and output for expansion. High impedance during RESET or IDLE modes.
When SPH is active (High), PXDATA(7:0) is controlled by the Host Interface. It will be high impedance except during
a Host read access, in which case it will be driven. The state of PXDATA(15:8) follows that of PXDATA(7:0) in this
case but is unused.
HEN
I
Active High Horizontal enable signal (HDelay starts counting from the rise of HEN)
VEN
I
Active High Verticle enable signal (VDelay starts counting from the rise of VEN)
SYSCLK
I
System clock (active on rising edge).
MADD(15:0)
O
Address output for the strip memory. Up to 64K x 16 bits of SRAM is addressable.
MDATA(15:0)
B
Data bus for the strip memory. Memory A is assigned to MDATA(7:0), and Memory B is assigned to MDATA(15:8).
MWE
O
Active Low: Write enable for the Strip Memory.
MOE
O
Active Low: Output enable for the Strip Memory.
DSYNC
B
Active Low: Sync. signal for 64 byte block of data. Output during compression and input during expansion. In
compression, DSYNC marks the start of an 8x8 image data block and should appear as an output one SYSCLK cycle
before the first image data of a block. During expansion DSYNC is input on SYSCLK before the first image data of
a sample block. The width of DSYNC is one SYSCLK. (Connect directly to ZR36050 DSYNC signal).
STOP
B
Active Low: Stop sending/receiving. During compression, this signal is an input which indicates that the CODEC is
busy, and the ZR36015 should stop sending data. During expansion, this signal is an output indicating the ZR36015
is not ready to receive data, and for the CODEC to stop sending data. (Connect directly to ZR36050 STOP signal).
EOS
B
Active Low: Signal indicates the end of each scan. Output during compression and input during expasion. In
compression, EOS is output together with the last image data sample of the last block of each scan. In expansion,
EOS is input together with the last image data sample of the last block of each scan. (Connect directly to ZR36050
EOS signal).
BDATA(7:0)
B/Z
Data bus interface with the Coder. Output for compression and input for expansion. High impedance during reset.
Otherwise, the direction of the bus is determined by the COE input. (Connect directly to ZR36050 PIXEL(11:4) bus.)
ADD(1:0)
I
Address select for Host access to internal registers. Enabled when SPH is high.
WR
I
Active Low: Write strobe for Host loading of internal registers and tables. Data is writtern on the rising edge of WR.
WR is enabled when SPH is high.
RD
I
Active Low: Read strobe for Host reading of internal registers and tables. RD is enabled when SPH is high.
CBSY
O
Active Low: CBSY indicates that the ZR36015 is not ready for the next strip of data.
COE
I
Coder bus output enable signal. HIGH for Compression Mode (enabling the output drivers for the CDATA bus, EOS
signal and DSYNC signal. . LOW for Expansion mode (enabling the output drivers for the STOP signal). (Connect
directly to ZR36050 COMP signal).
BSY
O
Active Low: BSY is active when the ZR36015 is processing an image. Before setting hte GO bit in the Mode Register,
BSY should be inactive.
CLKCSC
O
Clock output for ZR36011 Color Space Converter. Used to synchronize data transfers.
SPH
I
Active High: Select host access to the ZR36015 via the PXDATA(7:0) data bus. Enables the WR, RD inputs.
WINDOW
O
Active HIGH; Indicates active (windowed) image area.
RESET
I
Asynchronous Active LOW reset. All bi-directional signals are tri-stated when this signal is active. After RESET , the
ZR36015 will be in idle mode (GO bit cleared) and the PXDATA bus will continue to behigh impedance until the GO
bit is set .
V
DD
—
Power terminal.
V
SS
—
Ground terminal.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ZR36016 | INTEGRATED COLOR SPACE / RASTER-TO-BLOCK CONVERTER |
| ZR36016PQC-30 | INTEGRATED COLOR SPACE / RASTER-TO-BLOCK CONVERTER |
| ZR36016 | JPEG Pre- and Post-Processor(JPEG 先-后處理器) |
| ZR36050 | JPEG Image Compression Processor(JPEG 圖象壓縮處理器) |
| ZR36060 | Integrated JPEG Codec(集成JPEG編解碼器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ZR36016 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:INTEGRATED COLOR SPACE / RASTER-TO-BLOCK CONVERTER |
| ZR36016PQC | 制造商:ZORAN 功能描述: |
| ZR36016PQC-30 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:INTEGRATED COLOR SPACE / RASTER-TO-BLOCK CONVERTER |
| ZR36050 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:JPEG IMAGE COMPRESSION PROCESSOR |
| ZR36050PQC-21 | 制造商:ZORAN 功能描述: |
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