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參數(shù)資料
| 型號： | ZR36015PQC-30 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 元件分類： | 圓形連接器 |
| 英文描述： | Circular Connector; No. of Contacts:10; Series:; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:12; Circular Contact Gender:Pin; Circular Shell Style:Cable Receptacle; Insert Arrangement:12-10 |
| 中文描述： | 光柵座轉(zhuǎn)爐 |
| 文件頁數(shù)： | 23/27頁 |
| 文件大小： | 164K |
| 代理商： | ZR36015PQC-30 |
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ZR36015
23
PRELIMINARY
Figure 1. AC TESTING INPUT, OUTPUT
DEVICE
UNDER TEST
1.5V
1.5V
2.0V
0.45V
OUTPUT
INPUT
Figure 1. NORMAL AC TEST LOAD
Test Point
From Output
Under Test
50pF
A.C. testing, inputs are driven at 2.4V for a logic “1” and 0.45V for a logic “0”. Input
and output timing measurements are made a t 1.5V for both logic “1” and “0”.
1. T
IH
and T
IS
are for the following input signals: PXDATA (15:0), HEN, VEN, DSYNC, STOP, EOS, BDATA
2. Assumes WINDOW signal is high.
3. Measured during clock cycle when WINDOW goes high.
4. Measured from either rise of MWE, or fall of MOE.
5. Time during which MWE = low, and MOE = high.
6. Measured from start of time when MWE = low, and MOE = High.
53
Host Address Setup
tbd
ns
54
Host Address Hold
tbd
ns
55
Minimum Non-Active Time Between Host Read or Write
tbd
ns
56
Minimum Time After Fall of SPH to 1st Read or Write
tbd
ns
58
Host Read Address Hold Time
tbd
ns
59
Host Write Data Valid
tbd
ns
60
Host Write Data Hold
tbd
ns
61
Host Read Data Enable
tbd
ns
62
Host Read Data Valid
tbd
ns
63
Host Read Data Hold
tbd
ns
64
Host Read Data Disable
tbd
ns
70
Propagation Delay for CSCCLK
tbd
ns
Signal
Number
Description
Min
Max
Units
Test Conditions
Figure 1. System Clock Timing
SYSCLK
0.8V
1.5V
2.0V
1
2
3
5
2.0V
1.5V
0.8V
4
RESET
11
Figure 1. RESET Pulse Width
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相關代理商/技術參數(shù) |
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|---|---|
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