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參數(shù)資料
| 型號(hào)： | ZL50418 |
| 廠商： | Zarlink Semiconductor Inc. |
| 英文描述： | Managed 16-Port 10/100 M + 2-Port 1 G Ethernet Switch |
| 中文描述： | 管理16端口10/100平方米端口1個(gè)G以太網(wǎng)交換機(jī) |
| 文件頁數(shù)： | 21/163頁 |
| 文件大?。?/td> | 2122K |
| 代理商： | ZL50418 |
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ZL50418
Data Sheet
21
Zarlink Semiconductor Inc.
4.0 Memory Interface
4.1 Overview
The ZL50418 provides two 64-bit-wide SRAM banks, SRAM Bank A and SRAM Bank B with a 64-bit bus connected
to each. Each DMA can read and write from both bank A and bank B. The following figure provides an overview of
the ZL50418 SRAM banks.
Figure 6 - ZL50418 SRAM Interface Block Diagram (DMAs for 10/1000 Ports Only)
4.2 Detailed Memory Information
Because the bus for each bank is 64 bits wide, frames are broken into 8-byte granules, written to and read from
memory. The first 8-byte granule gets written to Bank A, the second 8-byte granule gets written to Bank B, and so
on in alternating fashion. When reading frames from memory, the same procedure is followed, first from A, then
from B, and so on.
The reading and writing from alternating memory banks can be performed with minimal waste of memory
bandwidth. What’s the worst case For any speed port, in the worst case, a 1-byte-long EOF granule gets written
to Bank A. This means that a 7-byte segment of Bank A bandwidth is idle, and furthermore, the next 8-byte
segment of Bank B bandwidth is idle, because the first 8 bytes of the next frame will be written to Bank A, not B.
This scenario results in a maximum 15 bytes of waste per frame, which is always acceptable because the
interframe gap is 20 bytes.
The CPU management port gets treated like any other port, reading and writing to alternating memory banks
starting with Bank A. The VLAN Index Mapping Table and Mac Address Table are duplicated in Bank A and B.
When the CPU writes an entry to the VLAN Index Mapping Table it has to write the same data in bank A and bank
B. Search engine data is written to both banks in parallel. In this way, a search engine read operation can be
performed by either bank at any time without a problem.
SRAM Bank A
TXDMA
0-7
TXDMA
8-15
RXDMA
0-7
RXDMA
8-15
SRAM Bank B
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ZL50418GKC | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Managed 16-Port 10/100 M + 2-Port 1 G Ethernet Switch |
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| ZL5V6B | 制造商:YEASHIN 制造商全稱:YEASHIN 功能描述:500 mW DO-35 Hermetically Sealed Glass Zener Voltage Regulators |
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