參數資料
型號： ZL50418
廠商： Zarlink Semiconductor Inc.
英文描述： Managed 16-Port 10/100 M + 2-Port 1 G Ethernet Switch
中文描述： 管理16端口10/100平方米端口1個G以太網交換機
文件頁數： 14/163頁
文件大?。?/td> 2122K
代理商： ZL50418
ZL50418
Data Sheet
14
Zarlink Semiconductor Inc.
1.4 10/100 MAC Module (RMAC)
The 10/100 Media Access Control module provides the necessary buffers and control interface between the Frame
Engine (FE) and the external physical device (PHY). The ZL50418 has two interfaces, RMII or Serial (only for
10 M). The 10/100 MAC of the ZL50418 device meets the IEEE 802.3 specification. It is able to operate in either
Half or Full Duplex mode with a back pressure/flow control mechanism. In addition, it will automatically retransmit
upon collision for up to 16 total transmissions. The PHY addresses for 16 10/100 MAC are from 08h to 1Fh.
1.5 CPU Interface Module
One extra port is dedicated to the CPU via the CPU interface module. The CPU interface utilizes a 16/8-bit bus in
managed mode (Bootstrap TSTOUT6 makes the selection). It also supports a serial and an I
2
C interface, which
provides an easy way to configure the system if unmanaged.
1.6 Management Module
The CPU can send a control frame to access or configure the internal network management database. The
Management Module decodes the control frame and executes the functions requested by the CPU.
1.7 Frame Engine
The main function of the frame engine is to forward a frame to its proper destination port or ports. When a frame
arrives, the frame engine parses the frame header (64 bytes) and formulates a switching request which is sent to
the search engine to resolve the destination port. The arriving frame is moved to the FDB. After receiving a switch
response from the search engine, the frame engine performs transmission scheduling based on the frame’s priority.
The frame engine forwards the frame to the MAC module when the frame is ready to be sent.
1.8 Search Engine
The Search Engine resolves the frame’s destination port or ports according to the destination MAC address (L2) or
IP multicast address (IP multicast packet) by searching the database. It also performs MAC learning, priority
assignment and trunking functions.
1.9 LED Interface
The LED interface provides a serial interface for carrying 16+2 port status signals. It can also provide direct status
pins (6) for the two Gigabit ports.
1.10 Internal Memory
Several internal tables are required and are described as follows:
Frame Control Block (FCB) - Each FCB entry contains the control information of the associated frame
stored in the FDB, e.g., frame size, read/write pointer, transmission priority, etc.
Network Management (NM) Database - The NM database contains the information in the statistics counters
and MIB.
MAC address Control Table (MCT) Link Table - The MCT Link Table stores the linked list of MCT entries that
have collisions in the external MAC Table.
Note
that the external MAC table is located in the external SSRAM Memory.
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