參數(shù)資料
型號(hào)： ZL50418
廠商： Zarlink Semiconductor Inc.
英文描述： Managed 16-Port 10/100 M + 2-Port 1 G Ethernet Switch
中文描述： 管理16端口10/100平方米端口1個(gè)G以太網(wǎng)交換機(jī)
文件頁數(shù)： 15/163頁
文件大?。?/td> 2122K
代理商： ZL50418
ZL50418
Data Sheet
15
Zarlink Semiconductor Inc.
2.0 System Configuration
2.1 Management and Configuration
Two modes are supported in the ZL50418: managed and unmanaged. In managed mode, the ZL50418 uses an 8
or 16 bit CPU interface very similar to the Industry Standard Architecture (ISA) specification. In unmanaged mode,
the ZL50418 has no CPU but can be configured by EEPROM using an I
2
C interface at bootup or via a synchronous
serial interface otherwise.
2.2 Managed Mode
In managed mode, the ZL50418 uses an 8 or 16 bit CPU interface very similar to the ISA bus. The ZL50418 CPU
interface provides for easy and effective management of the switching system. Figure 1 provides an overview of the
CPU interface.
Figure 2 - Overview of the CPU Interface
2.3 Register Configuration, Frame Transmission, and Frame Reception
2.3.1 Register Configuration
The ZL50418 has many programmable parameters covering such functions as QoS weights, VLAN control and port
mirroring setup. In managed mode, the CPU interface provides an easy way of configuring these parameters. The
parameters are contained in 8-bit configuration registers. The ZL50418 allows indirect access to these registers, as
follows:
If operating in 8 bits-interface mode, two “index” registers (addresses 000 and 001) need to be written, to
indicate the desired 8-bit register address. In 16-bit mode, only one register (address 000) needs to be
written for the desired 16-bit register address.
To indirectly configure the register addressed by the two index registers, a “configure data” register (address
010) must be written with the desired 8-bit data.
INDEX REG 1
(Addr = 001)
INDEX REG 0
(Addr = 000)
CONFIG
DATA REG
(Addr = 010)
FRAME DATA REG
(Addr = 011)
CONTROL
BLOCK REG
CPU
FRAME
RECEIVE
FIFO
CPU
FRAME
TRANSMIT
FIFO
CONTROL
COMMAND
FRAME
RECEIVE
FIFO
CONTROL
COMMAND
FRAME
TRANSMIT
FIFO
1 AND 2
INTERNAL
CONFIGUE
REGISTERS
SYNCHRONOUS
SERIAL
INTERFACE
8/16 bit internal
data bus
8/16 bit internal
data bus
8 bit
internal data bus
16 bit internal
address bus
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