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Data Sheet
ZL50212
9
Zarlink Semiconductor Inc.
1.0
Single Echo Voice Processor (EVP) Description
Each single Echo Voice Processor (EVP) contains 32 echo cancellers divided into 16 groups. Each group has two
echo cancellers, Echo Canceller A (ECA) and Echo Canceller B (ECB). Each group can be configured in Normal,
Extended Delay or Back-to-Back configurations. In
Normal configuration
, a group of echo cancellers provides two
channels of 64ms echo cancellation, which run independently on different channels. In
Extended Delay
configuration, a group of echo cancellers achieves 128ms of echo cancellation by cascading the two echo cancellers
(A & B). In
Back-to-Back
configuration, the two echo cancellers from the same group are positioned to cancel echo
coming from both directions in a single channel, providing full-duplex 64ms echo cancellation.
Each Echo Voice Processor contains the following main elements (see Figure 4).
Each echo canceller in the EVP has four functional states: Mute, Bypass, Disable Adaptation and Enable Adaptation.
These are explained in the section entitled Echo Canceller Functional States.
Adaptive Filter for estimating the echo channel
Subtractor for cancelling the echo
Double-Talk detector for disabling the filter adaptation during periods of double-talk
Path Change detector for fast reconvergence on major echo path changes
Instability Detector to combat instability in very low ERL environments
Patented Advanced Non-Linear Processor for suppression of residual echo, with comfort noise injection
Disable Tone Detectors for detecting valid disable tones at send and receive path inputs
Narrow-Band Detector for preventing Adaptive Filter divergence from narrow-band signals
Offset Null filters for removing the DC component in PCM channels
0 to -12dB level adjusters at all signal ports
Parallel controller interface compatible with Motorola microcontrollers
PCM encoder/decoder compatible with
μ
/A-Law ITU-T G.711 or Sign-Magnitude coding
Figure 4 - Functional Block Diagram of an Echo Canceller
Σ
Non-Linear
Processor
Offset
Null
Linear/
μ
/A-Law
Microprocessor
Interface
Double - Talk
Detector
C
Narrow-Band
Detector
μ
/A-Law/
Linear
Offset
Null
Echo Canceller (N), where 0 < N < 31
Sout
Rin
Sin
Rout
-
Programmable Bypass
(channel N)
(channel N)
(channel N)
(channel N)
ST-BUS
PORT1
ST-BUS
PORT2
MuteR
MuteS
0 to -12dB
Level Adjust
Linear/
μ
/A-Law
0 to -12dB
Level Adjust
0 to -12dB
Level Adjust
μ
/A-Law/
Linear
0 to -12dB
Level Adjust
A
F
Disable Tone
Detector
Disable Tone
Detector
Detector
Path Change
Instability
Detector