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ZL50212
Data Sheet
28
Zarlink Semiconductor Inc.
9.0
EVP Registers Description
Note: In order to correctly write to Control Register 1 and 2 of ECB, it is necessary to write the data twice to the register, one
immediately after another. The two writes must be separated by at least 350ns and no more than 20us.
Echo Canceller A (ECA): Control Register 1
Power-up 00
hex
Bit 6
INJDis
R/W Address: 00
hex
+ Base Address
Bit 3
Bit 2
Bypass
AdpDis
Bit 7
Reset
Bit 5
BBM
Functional Description of Register Bits
When high, the power-up initialization is executed. This presets all register bits including
this bit and clears the Adaptive Filter coefficients.
When high, the noise injection process is disabled. When low noise injection is enabled.
Bit 4
PAD
Bit 1
0
Bit 0
ExtDI
Reset
INJDis
BBM
When high, the Back to Back configuration is enabled. When low, the Normal
configuration is enabled. Note: Do not enable Extended-Delay and BBM configurations at
the same time. Always set
both
BBM bits of the two echo cancellers (Control Register 1)
of the same group to the same logic value to avoid conflict.
PAD
When high, 12dB of attenuation is inserted into the Rin to Rout path. When low, the Gains
register controls the signal levels.
When high, Sin data is by-passed to Sout and Rin data is by-passed to Rout. The
Adaptive Filter coefficients are set to zero and the filter adaptation is stopped. When low,
output data on both Sout and Rout is a function of the echo canceller algorithm.
When high, echo canceller adaptation is disabled. The Voice Processor cancels echo.
When low, the echo canceller dynamically adapts to the echo path characteristics.
Bits marked as “1” or “0” are reserved bits and should be written as indicated.
When high, Echo Cancellers A and B of the same group are internally cascaded into one
128ms echo canceller. When low, Echo Cancellers A and B of the same group operate
independently.
Bypass
AdpDis
0
ExtDl
Echo Canceller B (ECB): Control Register 1
Power-up 02
hex
Bit 6
INJDis
R/W Address: 20
hex
+ Base Address
Bit 3
Bit 2
Bypass
AdpDis
Bit 7
Reset
Bit 5
BBM
Functional Description of Register Bits
When high, the power-up initialization is executed which presets all register bits including
this bit and clears the Adaptive Filter coefficients.
When high, the noise injection process is disabled. When low, noise injection is enabled.
Bit 4
PAD
Bit 1
1
Bit 0
0
Reset
INJDis
BBM
When high, the Back to Back configuration is enabled. When low, the Normal
configuration is enabled. Note: Do not enable Extended-Delay and BBM configurations at
the same time. Always set
both
BBM bits of the two echo cancellers (Control Register 1)
of the same group to the same logic value to avoid conflict.
PAD
When high, 12dB of attenuation is inserted into the Rin to Rout path. When low, the Gains
register controls the signal levels.
When high, Sin data is by-passed to Sout and Rin data is by-passed to Rout. The
Adaptive Filter coefficients are set to zero and the filter adaptation is stopped. When low,
output data on both Sout and Rout is a function of the echo canceller algorithm.
When high, echo canceller adaptation is disabled. The Voice Processor cancels echo.
When low, the echo canceller dynamically adapts to the echo path characteristics.
Bits marked as “1” or “0” are reserved bits and should be written as indicated.
Control Register 1 (Echo Canceller B) Bit 0 is a reserved bit and should be written “0”.
Bypass
AdpDis
1
0