參數(shù)資料
型號(hào): ZL50015GAC
廠商: ZARLINK SEMICONDUCTOR INC
元件分類: 路由/交換
英文描述: Enhanced 1 K Digital Switch with Stratum 4E DPLL
中文描述: TELECOM, DIGITAL TIME SWITCH, PBGA256
封裝: 17 X 17 MM, 1.61 MM HEIGHT, PLASTIC, MS-034, BGA-256
文件頁數(shù): 118/122頁
文件大小: 926K
代理商: ZL50015GAC
ZL50015
Data Sheet
118
Zarlink Semiconductor Inc.
Characteristics are over recommended operating conditions unless otherwise stated.
Typical figures are at 25
°
C and are for design aid only: not guaranteed and not subject to production testing.
* See “Performance Characteristics Notes” on page 119.
DPLL Performance Characteristics
- Output Jitter Generation (Unfiltered except for CKo5)
Characteristics
Typ.
Units
Conditions/Notes*
1
Jitter at CKo0 and CKo3 (4.096 MHz)
810
ps-pp
1-6,14
2
Jitter at CKo1 and CKo3 (8.192 MHz)
800
ps-pp
3
Jitter at CKo2 and CKo3 (16.384 MHz)
710
ps-pp
4
Jitter at CKo3 (4.096, 8.192, 16.384, or 32.768 MHz)
670
ps-pp
5
Jitter at CKo4 (1.544 MHz or 2.048 MHz)
1.544 MHz
2.048 MHz
1060
630
ps-pp
ps-pp
6
Jitter at CKo5 (19.44 MHz)
unfiltered jitter
500 Hz - 1.3 MHz jitter
65 kHz - 1.3 MHz jitter
12 kHz - 1.3 MHz jitter
770
540
460
510
ps-pp
ps-pp
ps-pp
ps-pp
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