參數(shù)資料
型號(hào)： ZL30105
廠商： Zarlink Semiconductor Inc.
英文描述： Power Clamp On Multimeter; DMM Type:Clamp; No. of Digits/Alpha:3-3/4; DMM Response Type:True RMS; Approval Categories:CAT III 600V; Calibrated:No; Current Measuring Range:0-400.0A; Current Setting AC:400A RoHS Compliant: NA
中文描述： T1/E1/SDH層3冗余系統(tǒng)時(shí)鐘Synchonizer為AdvancedTCA和H.110
文件頁數(shù)： 34/50頁
文件大?。?/td> 691K
代理商： ZL30105
ZL30105
Data Sheet
34
Zarlink Semiconductor Inc.
5.5 Clock Redundancy System Architecture
Carrier-Class Telecommunications Equipment deployed in today’s networks guarantee better than 99.999%
operational availability (equivalent to less than 7 minutes of downtime per year). This high level of uninterrupted
service is achieved by fully redundant architectures with hot swappable cards like an ECTF H.110 or a PICMG
AdvancedTCA compliant system. Timing for these types of systems can be generated by the ZL30105 which
supports primary/secondary master timing protection switching.
The architecture shown in Figure 24 and Figure 25 is based on the ZL30105 being deployed on two separate timing
cards; the primary master timing card and the secondary master timing card. In normal operation the primary
master timing card receives synchronization from the network and provides timing for the whole system. The
redundant secondary master timing card is phase locked to the backplane clock and frame pulse through its REF2
and REF2_SYNC inputs. These two designated inputs allow the secondary master timing card to track the primary
master timing card clocks with minimal phase skew. When the primary master timing card fails unexpectedly (this
failure is not related to reference failure) then all switch cards or line cards will detect this failure and they will switch
to the timing supplied by the secondary master timing card. The secondary master timing card will be promoted to
primary master and switch from using the REF2 and REF2_SYNC inputs to one of the REF0 or REF1 inputs.
Figure 24 - Typical Clocking Architecture of an ECTF H.110 System
ZL30105
REF0
REF1
REF2
Primary Master Timing Card
MT90866
H.110 DX
Backplane
REF2_SYNC
C8o
F8o
CT_C8_A
CT_FRAME_A
CT_C8_B
CT_FRAME_B
CT_NETREF_1
CT_NETREF_2
SEC_MSTR
Master/Slave
Control
0
ZL30105
REF0
REF1
REF2
Secondary Master Timing Card
REF2_SYNC
C8o
F8o
SEC_MSTR
Master/Slave
Control
1
MT90866
H.110 DX
相關(guān)PDF資料
PDF描述
ZL30105QDG Digital Clamp-On Meter; DMM Type:Clamp; No. of Digits/Alpha:3-3/4; DMM Response Type:True RMS; Calibrated:No; Current Setting AC:1000A; Resistance Measuring Range:400 Ohm to 10 MOhm; Voltage Measuring Range AC:600V RoHS Compliant: NA
ZL30106QDG1 SONET/SDH/PDH Network Interface DPLL
ZL30106 SONET/SDH/PDH Network Interface DPLL
ZL30106QDG SONET/SDH/PDH Network Interface DPLL
ZL30107 GbE Line Card Synchronizer
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ZL30105_05 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:T1/E1/SDH Stratum 3 Redundant System Clock Synchronizer for AdvancedTC TM and H.110
ZL30105QDG 制造商:Zarlink Semiconductor Inc 功能描述:CLOCK SYNTHESIZER 64TQFP - Bulk
ZL30105QDG1 制造商:Microsemi Corporation 功能描述:CLOCK SYNTHESIZER 64TQFP - Trays 制造商:Microsemi Corporation 功能描述:IC Pb Free T1/E1 System Synchronizer 制造商:Zarlink Semiconductor Inc 功能描述:CLOCK SYNTHESIZER 64TQFP - Trays 制造商:Zarlink Semiconductor Inc 功能描述:IC Pb Free T1/E1 System Synchronizer
ZL30106 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:SONET/SDH/PDH Network Interface DPLL
ZL30106_05 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:SONET/SDH/PDH Network Interface DPLL
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*