參數(shù)資料
型號： ZL30105
廠商： Zarlink Semiconductor Inc.
英文描述： Power Clamp On Multimeter; DMM Type:Clamp; No. of Digits/Alpha:3-3/4; DMM Response Type:True RMS; Approval Categories:CAT III 600V; Calibrated:No; Current Measuring Range:0-400.0A; Current Setting AC:400A RoHS Compliant: NA
中文描述： T1/E1/SDH層3冗余系統(tǒng)時鐘Synchonizer為AdvancedTCA和H.110
文件頁數(shù)： 13/50頁
文件大?。?/td> 691K
代理商： ZL30105
ZL30105
Data Sheet
13
Zarlink Semiconductor Inc.
Figure 7 - Out-of-Range Thresholds for APP_SEL=10 and APP_SEL=11
In addition to the monitoring of the REF2 reference signal the companion REF2_SYNC input signal is also
monitored for failure (see Figure 8).
Sync Ratio Monitor (SRM)
: This monitor detects if the REF2_SYNC signal is a 2 kHz or an 8 kHz signal. It also
checks the number of REF2 reference clock cycles in a single REF2_SYNC frame pulse period to determine the
integrity of the REF2_SYNC signal, for example there must be exactly 256 clock cycles of a 2.048 MHz REF2
reference clock in a single REF2_SYNC 8 kHz frame pulse period to validate the REF2_SYNC signal. If the REF2
and REF2_SYNC inputs are selected for synchronization and the Sync Ratio Monitor detects a failure, the DPLL
will abandon the mechanism of aligning the output frame pulse to the REF2_SYNC pulse. Instead only the REF2
reference will be used for synchronization.
Figure 8 - REF2_SYNC Reference Monitor
2.3 Time Interval Error (TIE) Corrector Circuit
The TIE Circuit eliminates phase transients on the output clock that may occur during reference switching or the
recovery from Holdover mode to Normal mode.
On recovery from Holdover mode (dependent on the HMS pin) or when switching to another reference input, the
TIE corrector circuit measures the phase delay between the current phase (feedback signal) and the phase of the
selected reference signal. This delay value is stored in the TIE corrector circuit. This circuit creates a new virtual
reference signal that is at the same phase position as the feedback signal. By using the virtual reference, the PLL
minimizes the phase transient it experiences when it recovers from Holdover mode.
0 ppm
+4.6 ppm
-4.6 ppm
0
7.4
12
9.2
4.6
4.6
-4.6
-13.8
-15
-10
0
-5
5
15
Frequency offset [ppm]
Out of Range
Out of Range
Out of Range
In Range
In Range
In Range
C20
10
-9.2
-12
16.6
13.8
-4.6
-7.4
-16.6
C20: 20 MHz master oscillator clock
C20
C20
C20 Clock Accuracy
SYNC
Reference
Monitor
Circuit
to DPLL
REF2_SYNC
REF2
frequency
REF2
相關(guān)PDF資料
PDF描述
ZL30105QDG Digital Clamp-On Meter; DMM Type:Clamp; No. of Digits/Alpha:3-3/4; DMM Response Type:True RMS; Calibrated:No; Current Setting AC:1000A; Resistance Measuring Range:400 Ohm to 10 MOhm; Voltage Measuring Range AC:600V RoHS Compliant: NA
ZL30106QDG1 SONET/SDH/PDH Network Interface DPLL
ZL30106 SONET/SDH/PDH Network Interface DPLL
ZL30106QDG SONET/SDH/PDH Network Interface DPLL
ZL30107 GbE Line Card Synchronizer
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ZL30105_05 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:T1/E1/SDH Stratum 3 Redundant System Clock Synchronizer for AdvancedTC TM and H.110
ZL30105QDG 制造商:Zarlink Semiconductor Inc 功能描述:CLOCK SYNTHESIZER 64TQFP - Bulk
ZL30105QDG1 制造商:Microsemi Corporation 功能描述:CLOCK SYNTHESIZER 64TQFP - Trays 制造商:Microsemi Corporation 功能描述:IC Pb Free T1/E1 System Synchronizer 制造商:Zarlink Semiconductor Inc 功能描述:CLOCK SYNTHESIZER 64TQFP - Trays 制造商:Zarlink Semiconductor Inc 功能描述:IC Pb Free T1/E1 System Synchronizer
ZL30106 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:SONET/SDH/PDH Network Interface DPLL
ZL30106_05 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:SONET/SDH/PDH Network Interface DPLL
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