參數(shù)資料
型號(hào)： ZL30105
廠商： Zarlink Semiconductor Inc.
英文描述： Power Clamp On Multimeter; DMM Type:Clamp; No. of Digits/Alpha:3-3/4; DMM Response Type:True RMS; Approval Categories:CAT III 600V; Calibrated:No; Current Measuring Range:0-400.0A; Current Setting AC:400A RoHS Compliant: NA
中文描述： T1/E1/SDH層3冗余系統(tǒng)時(shí)鐘Synchonizer為AdvancedTCA和H.110
文件頁(yè)數(shù)： 20/50頁(yè)
文件大小： 691K
代理商： ZL30105
ZL30105
Data Sheet
20
Zarlink Semiconductor Inc.
3.4.2 Holdover Mode
Holdover Mode is typically used for short durations while network synchronization is temporarily disrupted.
In Holdover Mode, the ZL30105 provides timing and synchronization signals, which are not locked to an external
reference signal, but are based on storage techniques. The storage value is determined while the device is in
Normal Mode and locked to an external reference signal.
When in Normal Mode, and locked to the input reference signal, a numerical value corresponding to the ZL30105
output reference frequency is stored alternately in two memory locations every 26 ms. When the device is switched
into Holdover Mode, the value in memory from between 26 ms and 52 ms is used to set the output frequency of the
device. The frequency accuracy of Holdover Mode is 0.01 ppm.
Two factors affect the accuracy of Holdover mode. One is drift on the master clock while in Holdover mode, drift on
the master clock directly affects the Holdover mode accuracy. Note that the absolute master clock (OSCi) accuracy
does not affect Holdover accuracy, only the
change
in OSCi accuracy while in Holdover. For example, a
±
32 ppm
master clock may have a temperature coefficient of
±
0.1 ppm per °C. So a
±
10 °C change in temperature, while the
ZL30105 is in Holdover mode may result in an additional offset (over the 0.01 ppm) in frequency accuracy of
±
1 ppm. Which is much greater than the 0.01 ppm of the ZL30105. The other factor affecting the accuracy is large
jitter on the reference input prior to the mode switch.
3.4.3 Normal Mode
Normal mode is typically used when a system clock source, synchronized to the network is required. In Normal
mode, the ZL30105 provides timing (C1.5o, C2o, C4o, C8o, C16o, C19o, C32 and C65o) and frame
synchronization (F2ko, F4o, F8o, F16o, F32o and F65o) signals, which are synchronized to one of three reference
inputs (REF0, REF1 or REF2). The input reference signal may have a nominal frequency of 2 kHz, 8 kHz,
1.544 MHz, 2.048 MHz, 8.192 MHz, 16.384 MHz or 19.44 MHz. The frequency of the reference inputs are
automatically detected by the reference monitors.
When the ZL30105 comes out of RESET while Normal mode is selected by its MODE_SEL pins then it will initially
go into Holdover mode and generate clocks with the accuracy of its freerunning local oscillator (see Figure 12). If
the ZL30105 determines that its selected reference is disrupted (see Figure 3), it will remain in Holdover until the
selected reference is no longer disrupted or the external controller selects another reference that is not disrupted. If
the ZL30105 determines that its selected reference is not disrupted (see Figure 3) then the state machine will cause
the DPLL to recover from Holdover via one of two paths depending on the logic level at the HMS pin. If HMS=0 then
the ZL30105 will transition directly to Normal mode and it will align its output signals with its selected input
reference (see Figure 10). If HMS=1 then the ZL30105 will transition to Normal mode via the TIE correction state
and the phase difference between the output signals and the selected input reference will be maintained.
When the ZL30105 is operating in Normal mode, if it determines that its selected reference is disrupted (Figure 3)
then its state machine will cause it to automatically go to Holdover mode. When the ZL30105 determines that its
selected reference is not disrupted then the state machine will cause the DPLL to recover from Holdover via one of
two paths depending on the logic level at the HMS pin (see Figure 12). If HMS=0 then the ZL30105 will transition
directly to Normal mode and it will align its output signals with its input reference (see Figure 10). If HMS=1 then the
ZL30105 will transition to Normal mode via the TIE correction state and the phase difference between the output
signals and the input reference will be maintained.
If the reference selection changes because the value of the REF_SEL1:0 pins changes or because the reference
selection state machine selected a different reference input, the ZL30105 goes into Holdover mode and returns to
Normal mode through the TIE correction state regardless of the logic value on HMS pin.
ZL30105 provides a fast lock pin (FASTLOCK), which, when set high enables the PLL to lock to an incoming
reference within approximately 1 s.
相關(guān)PDF資料
PDF描述
ZL30105QDG Digital Clamp-On Meter; DMM Type:Clamp; No. of Digits/Alpha:3-3/4; DMM Response Type:True RMS; Calibrated:No; Current Setting AC:1000A; Resistance Measuring Range:400 Ohm to 10 MOhm; Voltage Measuring Range AC:600V RoHS Compliant: NA
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ZL30105_05 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:T1/E1/SDH Stratum 3 Redundant System Clock Synchronizer for AdvancedTC TM and H.110
ZL30105QDG 制造商:Zarlink Semiconductor Inc 功能描述:CLOCK SYNTHESIZER 64TQFP - Bulk
ZL30105QDG1 制造商:Microsemi Corporation 功能描述:CLOCK SYNTHESIZER 64TQFP - Trays 制造商:Microsemi Corporation 功能描述:IC Pb Free T1/E1 System Synchronizer 制造商:Zarlink Semiconductor Inc 功能描述:CLOCK SYNTHESIZER 64TQFP - Trays 制造商:Zarlink Semiconductor Inc 功能描述:IC Pb Free T1/E1 System Synchronizer
ZL30106 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:SONET/SDH/PDH Network Interface DPLL
ZL30106_05 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:SONET/SDH/PDH Network Interface DPLL
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