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參數(shù)資料
| 型號： | ZL30105 |
| 廠商： | Zarlink Semiconductor Inc. |
| 英文描述： | Power Clamp On Multimeter; DMM Type:Clamp; No. of Digits/Alpha:3-3/4; DMM Response Type:True RMS; Approval Categories:CAT III 600V; Calibrated:No; Current Measuring Range:0-400.0A; Current Setting AC:400A RoHS Compliant: NA |
| 中文描述： | T1/E1/SDH層3冗余系統(tǒng)時(shí)鐘Synchonizer為AdvancedTCA和H.110 |
| 文件頁數(shù)： | 11/50頁 |
| 文件大?。?/td> | 691K |
| 代理商： | ZL30105 |
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ZL30105
Data Sheet
11
Zarlink Semiconductor Inc.
Figure 3 - Reference Monitor Circuit
Exceeding the thresholds of any of the monitors forces the corresponding REF_FAIL pin to go high. The single
cycle and coarse frequency failure flags force the DPLL into Holdover mode and feed a timer that disqualifies the
reference input signal when the failures are present for more than 2.5 s. The single cycle and coarse frequency
failures must be absent for 10 s to let the timer re-qualify the input reference signal as valid. Multiple failures of less
than 2.5 s each have an accumulative effect and will disqualify the reference eventually. This is illustrated in Figure
4 where REF0 experiences disruptions while REF1 is stable.
Figure 4 - Behaviour of the Dis/Re-qualify Timer
Reference Frequency
Detector
Single Cycle
Monitor
Precise Frequency
Monitor
Coarse Frequency
Monitor
dis/requalify
timer
REF0 /
REF1 /
REF2
OR
OR
OR
REF_OOR = reference out of range.
REF_DIS= reference disrupted.
Both are internal signals.
Reference
select
state machine
REF_SEL1:0
REF_OOR
Mode select
state machine
HOLDOVER
REF_DIS
REF_FAIL0 /
REF_FAIL1 /
REF_FAIL2
2.5 s
10 s
REF0
dis/requalify
timer on REF0
SCM or CFM failure
REF_FAIL0
HOLDOVER
REF_OOR0
(internal signal)
REF1
REF0
REF1
REF0
REF_SEL
SCM or CFM failure
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ZL30105QDG | Digital Clamp-On Meter; DMM Type:Clamp; No. of Digits/Alpha:3-3/4; DMM Response Type:True RMS; Calibrated:No; Current Setting AC:1000A; Resistance Measuring Range:400 Ohm to 10 MOhm; Voltage Measuring Range AC:600V RoHS Compliant: NA |
| ZL30106QDG1 | SONET/SDH/PDH Network Interface DPLL |
| ZL30106 | SONET/SDH/PDH Network Interface DPLL |
| ZL30106QDG | SONET/SDH/PDH Network Interface DPLL |
| ZL30107 | GbE Line Card Synchronizer |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ZL30105_05 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:T1/E1/SDH Stratum 3 Redundant System Clock Synchronizer for AdvancedTC TM and H.110 |
| ZL30105QDG | 制造商:Zarlink Semiconductor Inc 功能描述:CLOCK SYNTHESIZER 64TQFP - Bulk |
| ZL30105QDG1 | 制造商:Microsemi Corporation 功能描述:CLOCK SYNTHESIZER 64TQFP - Trays 制造商:Microsemi Corporation 功能描述:IC Pb Free T1/E1 System Synchronizer 制造商:Zarlink Semiconductor Inc 功能描述:CLOCK SYNTHESIZER 64TQFP - Trays 制造商:Zarlink Semiconductor Inc 功能描述:IC Pb Free T1/E1 System Synchronizer |
| ZL30106 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:SONET/SDH/PDH Network Interface DPLL |
| ZL30106_05 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:SONET/SDH/PDH Network Interface DPLL |
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