參數(shù)資料
型號: XRT86VL38
廠商: Exar Corporation
元件分類: 通信及網(wǎng)絡(luò)
英文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁數(shù): 42/66頁
文件大?。?/td> 425K
代理商: XRT86VL38
XRT86VL38
39
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
REV. V1.2.0
JTAG INTERFACE
The XRT86VL38 device’s JTAG features comply with the IEEE 1149.1 standard. Please refer to the industry
specification for additional information on boundary scan operations.
S
IGNAL
N
AME
420 P
KG
B
ALL
#
484P
KG
B
ALL
#
T
YPE
O
UTPUT
D
RIVE
(
M
A)
D
ESCRIPTION
TCK
A7
F10
I
-
Test clock: Boundary Scan Test clock input:
The TCLK signal is the clock for the TAP controller, and it
generates the boundary scan data register clocking. The
data on TMS and TDI is loaded on the positive edge of
TCK. Data is observed at TDO on the falling edge of TCK.
TMS
A5
B6
I
-
Test Mode Select:
Boundary Scan Test Mode Select
input.
The TMS signal controls the transitions of the TAP con-
troller in conjunction with the rising edge of the test clock
(TCK).
N
OTE
:
For normal operation this pin must be pulled
’High’.
TDI
D7
E9
I
-
Test Data In:
Boundary Scan Test data input
The TDI signal is the serial test data input.
N
OTE
:
This pin is internally pulled ’high’.
TDO
B6
D8
O
8
Test Data Out:
Boundary Scan Test data output
The TDO signal is the serial test data output.
TRST
B7
A6
I
-
Test Reset Input:
The TRST signal (Active Low) asynchronously resets the
TAP controller to the Test-Logic-Reset state.
N
OTE
:
This pin is internally pulled ’high’
TEST
B11
E12
I
-
Factory Test Mode Pin
N
OTE
:
This pin is internally pulled ’low’, and should be
pulled ’low’ for normal operation.
aTEST
E7
C7
I
-
Factory Test Mode Pin
N
OTE
:
This pin is internally pulled ’low’, and should be
pulled ’low’ for normal operation.
JTAG_Ring
D4
C2
I
-
JTAG_Ring Test Pin
JTAG_Tip
F5
E5
I
-
JTAG_Tip Test Pin
相關(guān)PDF資料
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