參數(shù)資料
型號(hào): XRT86VL38
廠商: Exar Corporation
元件分類: 通信及網(wǎng)絡(luò)
英文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁(yè)數(shù): 39/66頁(yè)
文件大?。?/td> 425K
代理商: XRT86VL38
XRT86VL38
36
REV. V1.2.0
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
TxON
Y3
W1
I
Transmitter On
This input pin permits the user to either enable or disable the Trans-
mit Output Driver within the Transmit DS1/E1 LIU Block. If the TxON
pin is pulled “Low”, all 8 Channels are tri-stated. When this pin is
pulled ‘High’, turning on or off the transmitters will be determined by
the appropriate channel registers (address 0x0Fn2, bit 3)
LOW
= Disables the Transmit Output Driver within the Transmit DS1/
E1 LIU Block. In this setting, the TTIP and TRING output pins of all 8
channels will be tri-stated.
HIGH
= Enables the Transmit Output Driver within the Transmit DS1/
E1 LIU Block. In this setting, the corresponding TTIP and TRING out-
put pins will be enabled or disabled by programming the appropriate
channel register. (address 0x0Fn2, bit 3)
N
OTE
:
Whenever the transmitters are turned off, the TTIP and
TRING output pins will be tri-stated.
TIMING INTERFACE
S
IGNAL
N
AME
420 P
KG
B
ALL
#
484 P
KG
B
ALL
#
T
YPE
O
UTPUT
D
RIVE
(
M
A)
D
ESCRIPTION
MCLKIN
A4
A5
I
-
Master Clock Input:
This pin is used to provide the timing reference for the inter-
nal master clock of the device. The frequency of this clock
is programmable from 8kHz to 16.384MHz in register
0x0FE9.
E1MCLKnOUT
B5
A4
O
12
LIU E1 Output Clock Reference
This output pin is defaulted to 2.048MHz, but can be pro-
grammed to 4.096MHz, 8.192MHz, or 16.384MHz in regis-
ter 0x0FE4.
T1MCLKnOUT
D6
F9
O
12
LIU T1 Output Clock Reference
This output pin is defaulted to 1.544MHz, but can be pro-
grammed to output 3.088MHz, 6.176MHz, or 12.352MHz in
register 0x0FE4.
E1OSCCLK
Y5
V4
O
8
Framer E1 Output Clock Reference
This output pin is defaulted to 2.048MHz, but can be pro-
grammed to 65.536MHz in register 0x011E.
T1OSCCLK
AC1
V3
O
8
Framer T1 Output Clock Reference
This output pin is defaulted to 1.544MHz, but can be pro-
grammed to output 49.408MHz in register 0x011E.
8KSYNC
AB3
W2
O
8
8kHz Clock Output Reference
This pin is an output reference of 8kHz based on the
MCLKIN input. Therefore, the duty cycle of this output is
determined by the time period of the input clock reference.
TRANSMIT LINE INTERFACE
S
IGNAL
N
AME
420 P
KG
B
ALL
#
484 P
KG
B
ALL
#
T
YPE
D
ESCRIPTION
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