參數(shù)資料
型號: XRT83SL34IV
廠商: EXAR CORP
元件分類: 數(shù)字傳輸電路
英文描述: QUAD T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
中文描述: DATACOM, PCM TRANSCEIVER, PQFP128
封裝: 14 X 20 MM, 1.40 MM HEIGHT, TQFP-128
文件頁數(shù): 8/80頁
文件大?。?/td> 1154K
代理商: XRT83SL34IV
XRT83SL34
QUAD T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.0
13
ALARM FUNCTION//REDUNDANCY SUPPORT
MCLKT1
33
I
T1 Master Clock Input
This signal is an independent 1.544MHz clock for T1 systems with required
accuracy of better than ±50ppm and duty cycle of 40% to 60%. MCLKT1
input is used in the T1 mode.
NOTES:
1.
All channels of the XRT83SL34 must be operated at the same clock
rate, either T1, E1 or J1.
2.
See pin 32 description for further explanation for the usage of this
pin.
3.
Internally pulled “Low” with a 50k
resistor.
MCLKOUT
36
O
Synthesized Master Clock Output
This signal is the output of the Master Clock Synthesizer PLL which is at T1
or E1 rate based upon the mode of operation.
SIGNAL NAME
PIN #TYPE
DESCRIPTION
GAUGE
87
I
Twisted Pair Cable Wire Gauge Select - Hardware mode
Connect this pin "High" to select 26 Gauge wire. Connect this pin “Low” to
select 22 and 24 gauge wire for all channels.
NOTE: Internally pulled “Low” with a 50k
resistor.
DMO_0
DMO_1
DMO_2
DMO_3
64
65
66
67
O
Driver Failure Monitor Channel _0
This pin transitions "High" if a short circuit condition is detected in the trans-
mit driver of Channel _0, or no transmit output pulse is detected for more
than 128 TCLK_0 cycles.
Driver Failure Monitor Channel _1
Driver Failure Monitor Channel _2
Driver Failure Monitor Channel _3
ATAOS
PCLK
50
I
Automatic Transmit “All Ones” Pattern - Hardware Mode
A "High" level on this pin enables the automatic transmission of an "All Ones"
AMI pattern from the transmitter of any channel that the receiver of that
channel has detected an LOS condition. A "Low" level on this pin disables
this function.
NOTE: All channels share the same ATAOS input control function.
Microprocessor Clock Input - Host Mode
NOTE: This pin is internally pulled “Low” for asynchronous microprocessor
interface when no clock is present.
SIGNAL NAME
PIN #TYPE
DESCRIPTION
相關(guān)PDF資料
PDF描述
XRT83SL34 QUAD T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
XS2F-A422-90-A 4 CONTACT(S), POLYBUTYLENE TEREPHTHALATE, FEMALE, CIRCULAR CONNECTOR, CLAMP, SOCKET
XS2F-A422-A90-A 4 CONTACT(S), POLYBUTYLENE TEREPHTHALATE, FEMALE, CIRCULAR CONNECTOR, CLAMP, SOCKET
XS2F-A422-AB0-A 4 CONTACT(S), POLYBUTYLENE TEREPHTHALATE, FEMALE, CIRCULAR CONNECTOR, CLAMP, SOCKET
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