參數(shù)資料
型號(hào): XRT83SL34IV
廠商: EXAR CORP
元件分類: 數(shù)字傳輸電路
英文描述: QUAD T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
中文描述: DATACOM, PCM TRANSCEIVER, PQFP128
封裝: 14 X 20 MM, 1.40 MM HEIGHT, TQFP-128
文件頁數(shù): 16/80頁
文件大小: 1154K
代理商: XRT83SL34IV
XRT83SL34
QUAD T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.0
20
RECEIVE MONITOR MODE
In applications where Monitor mode is desired, the equalizer can be configured in a gain mode which handles
input signals attenuated resistively up to 29dB, along with 0 to 6dB cable attenuation for both T1 and E1
applications, refer to Table 5 for details. This feature is available in both Hardware and Host modes.
RECEIVER LOSS OF SIGNAL (RLOS)
For compatibility with ITU G.775 requirements, the RLOS monitoring function is implemented using both
analog and digital detection schemes. If the analog RLOS condition occurs, a digital detector is activated to
count for 32 consecutive zeros in E1 (4096 bits in Extended Los mode, EXLOS = “1”) or 175 consecutive zeros
in T1 before RLOS is asserted. RLOS is cleared when the input signal rises +3dB (built in hysteresis) above
the point at which it was declared and meets 12.5% ones density of 4 ones in a 32 bit window, with no more
than 16 consecutive zeros for E1. In T1 mode, RLOS is cleared when the input signal rises +3dB (built in
hysteresis) above the point at which it was declared and contains 16 ones in a 128 bit window with no more
than 100 consecutive zeros in the data stream. When loss of signal occurs, RLOS register indication and
register status will change. If the RLOS register enable is set high (enabled), the alarm will trigger an interrupt
causing the interrupt pin (INT) to go low. Once the alarm status register has been read, it will automatically
reset upon read (RUR), and the INT pin will return high.
Analog RLOS
Setting the Receiver Inputs to -15dB T1/E1 Short Haul Mode
By setting the receiver inputs to -15dB T1/E1 short haul mode, the equalizer will detect the incoming amplitude
and make adjustments by adding gain up to a maximum of +15dB normalizing the T1/E1 input signal.
NOTE: This is the only setting that refers to cable loss (frequency), not flat loss (resistive).
Once the T1/E1 input signal has been normalized to 0dB by adding the maximum gain (+15dB), the receiver
will declare RLOS if the signal is attenuated by an additional -9dB. The total cable loss at RLOS declaration is
typically -24dB (-15dB + -9dB). A 3dB hysteresis was designed so that transients will not trigger the RLOS to
clear. Therefore, the RLOS will typically clear at a total cable attenuation of -21dB. See Figure 6 for a simplified
diagram.
Setting the Receiver Inputs to -29dB T1/E1 Gain Mode
By setting the receiver inputs to -29dB T1/E1 gain mode, the equalizer will detect the incoming amplitude and
make adjustments by adding gain up to a maximum of +29dB normalizing the T1/E1 input signal.
NOTE: This is the only setting that refers to flat loss (resistive). All other modes refer to cable loss (frequency).
Once the T1/E1 input signal has been normalized to 0dB by adding the maximum gain (+29dB), the receiver
will declare RLOS if the signal is attenuated by an additional -9dB. The total cable loss at RLOS declaration is
FIGURE 6. SIMPLIFIED DIAGRAM OF -15dB T1/E1 SHORT HAUL MODE AND RLOS CONDITION
Norm alized up to +15dB Max
Declare LOS
Clear LOS
-9dB
+3dB
Clear LOS
Declare LOS
+3dB
-9dB
相關(guān)PDF資料
PDF描述
XRT83SL34 QUAD T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
XS2F-A422-90-A 4 CONTACT(S), POLYBUTYLENE TEREPHTHALATE, FEMALE, CIRCULAR CONNECTOR, CLAMP, SOCKET
XS2F-A422-A90-A 4 CONTACT(S), POLYBUTYLENE TEREPHTHALATE, FEMALE, CIRCULAR CONNECTOR, CLAMP, SOCKET
XS2F-A422-AB0-A 4 CONTACT(S), POLYBUTYLENE TEREPHTHALATE, FEMALE, CIRCULAR CONNECTOR, CLAMP, SOCKET
XS2F-A422-AC0-A 4 CONTACT(S), POLYBUTYLENE TEREPHTHALATE, FEMALE, CIRCULAR CONNECTOR, CLAMP, SOCKET
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