XRT74L73
3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER
REV. P1.0.1
PRELIMINARY
27
M2
M1
N3
TxSer_0/
TxPOH_0/
SendMSG_0
TxSer_1/
TxPOH_1/
SendMSG_1
TxSer_2/
TxPOH_2/
SendMSG_2
I
Transmit Payload Data Serial Input/Transmit PLCP Path Overhead Input/
Send HDLC Message Request Input:
The function of this input pin depends upon whether the XRT74L73 device is
configured to operate in the Clear-Channel Framer Mode, the High-Speed HDLC
Controller Mode or in the ATM/PLCP Mode.
Clear-Channel Framer Mode - TxSer_n:
If the XRT74L73 device is configured to operate in the Clear-Channel Framer
mode, then this input pin functions as the "Transmit Payload Data Serial Input"
pin. In this case, the local terminal equipment is expected to apply all outbound
data (which is intended to be carried via the DS3 or E3 payload bits) to this input
pin.The Transmit Payload Data Input Interface will sample the data, residing at
the "TxSer_n" input pin, upon the rising edge of TxInClk.
ATM/PLCP Mode - TxPOH_n:
If the XRT74L73 device is configured to operate in the ATM Mode, and if (within
the ATM Mode, the chip is also configured to operate in the PLCP Mode), then
this input pin functions as the "Transmit PLCP Path Overhead Input Pin". In this
mode, the user can externally insert "desired" path overhead byte values into the
"outbound" PLCP frames.The Transmit PLCP Path Overhead Input Pin (and
Port) become active whenever the user asserts the "TxPOHIns" input pin (by
pulling it "high"). In this case, the data, residing upon the "TxPOH_n" input pin
will be sampled upon the rising edge of the "TxPOHClk" signal.
N
OTE
:
This input pin is inactive if the XRT74L73 device is configured to operate
in the Direct-Mapped ATM Mode.
High-Speed HDLC Controller Mode - SendMSG_n:
If the XRT74L73 device is configured to operate in the "High-Speed HDLC Con-
troller" Mode, then this input pin functions as the "Transmit HDLC Controller
Input Interface" enable input pin. If the user asserts this input pin (by pulling it
"high") then the "Transmit HDLC Controller Input Interface" will proceed to latch
the data, residing on the "TxHDLCDat[7:0]" input pins, upon each rising edge of
the "TxHDLCClk_n signal. All data that is latched into the "Transmit HDLC Con-
troller Input Interface" (for the duration that the "SendMSG_n" input pin is "high")
will be encapsulated into an HDLC frame and ultimately transported via the pay-
load bits of the outbound DS3 or E3 data stream. If the user pulling this input pin
"low", then the Transmit HDLC Controller Input Interface will cease latching the
data, residing on the TxHDLCDat[7:0] bus.
N
OTE
:
This input pin is inactive if the XRT74L73 device has been configured to
operate in the PPP Mode.
N1
N4
P3
TxPOHClk_0
TxPOHClk_1
TxPOHClk_2
O
Transmit PLCP Frame POH Byte Insertion Clock:
This pin, along with the TxPOH_n and the TxPOHMSB_n input pins, function as
the "Transmit PLCP Frame POH Byte" serial input port. This output pin func-
tions as a clock output signal that is be used to sample the user’s POH data at
the TxPOH_n input pin. This output pin is always active, independent of the
state of the "TxPOHIns" pin.
N
OTE
:
This pin is only active if the XRT74L73 device has been configured to
operate in the ATM/PLCP Mode.
PIN DESCRIPTION
P
IN
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N
AME
T
YPE
D
ESCRIPTION