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參數(shù)資料
| 型號： | XRT73R12IB |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 81/89頁 |
| 文件大小： | 0K |
| 描述： | IC LIU E3/DS3/STS-1 12CH 420TBGA |
| 標準包裝： | 40 |
| 類型： | 線路接口裝置（LIU） |
| 驅(qū)動器/接收器數(shù)： | 12/12 |
| 規(guī)程： | DS3，E3，STS-1 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 420-LBGA 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 420-TBGA（35x35） |
| 包裝： | 托盤 |
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XRT73R12
79
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.0.3
1
STS-1/
DS3_n
R/W
STS-1/DS3 Mode Select - Channel_n:
This READ/WRITE bit-field, along with Bit 2 (E3_n) is used to configure a
given channel into either the DS3, E3 or STS-1 Modes.
This bit-field is ignored if Bit 2 (E3_n) has been set to "1".
If Bit 2 (E3_n) is a 0:
0 - Configures Channel_n to operate in the DS3 Mode.
1 - Configures Channel_n to operate in the STS-1 Mode .
0
SR/DR_n
R/W
Single-Rail/Dual-Rail Select - Channel_n:
This READ/WRITE bit-field is used to configure Channel_n to operate in
either the Single-Rail or Dual-Rail Mode.
If the user configures the Channel to operate in the Single-Rail Mode, the
following will happen.
The B3ZS/HDB3 Encoder and Decoder blocks (within Channel_n) will be
enabled.
The Transmit Section of Channel_n will accept all of the outbound data
(from the System-side Equipment) via the TxPOS_n input pin.
The Receive Section of each channel will output all of the recovered data
(to the System-side Equipment) via the RxPOS_n output pin.
The corresponding RNEG/LCV_n output pin will now function as the LCV
(Line Code Violation or Excessive Zero Event) indicator output pin for
Channel_n.
If the user configures Channel_n to operate in the Dual-Rail Mode, the fol-
lowing will happen.
The B3ZS/HDB3 Encoder and Decoder blocks of Channel_n will be
disabled.
The Transmit Section of Channel_n will be configured to accept positive-
polarity data via the TxPOS_n input pin and negative-polarity data via the
TxNEG_n input pin.
The Receive Section of Channel_n will pulse the RxPOS_n output pin
"High" (for one period of RCLK_n) for each time a positive-polarity pulse is
received via the RTIP_n/RRING_n input pins.
Likewise, the Receive
Section of each channel will pulse the RxNEG_n output pin "High" (for
one period of RxCLK_n) for each time a negative-polarity pulse is
received via the RTIP_n/RRING_n input pins.
0 - Configures Channel_n to operate in the Dual-Rail Mode.
1 - Configures Channel_n to operate in the Single-Rail Mode.
TABLE 39: CHANNEL CONTROL REGISTER - CHANNEL N ADDRESS LOCATION = 0XM6
(N = [0:11] & M= 0-5 & 8-D)
BIT NUMBER
NAME
TYPE
DESCRIPTION
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