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參數(shù)資料
| 型號： | XRT73R12IB |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 46/89頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC LIU E3/DS3/STS-1 12CH 420TBGA |
| 標準包裝： | 40 |
| 類型： | 線路接口裝置（LIU） |
| 驅動器/接收器數(shù)： | 12/12 |
| 規(guī)程： | DS3，E3，STS-1 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 420-LBGA 裸露焊盤 |
| 供應商設備封裝： | 420-TBGA（35x35） |
| 包裝： | 托盤 |
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XRT73R12
47
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.0.3
7.2
ASYNCHRONOUS AND SYNCHRONOUS DESCRIPTION
Whether the LIU is configured for Asynchronous or Synchronous mode, the following descriptions apply. The
synchronous mode requires an input clock (PCLK) to be used as the microprocessor timing reference. Read
and Write operations are described below.
Read Cycle (For Pmode = "0" or "1")
Whenever the local P wishes to read the contents of a register, it should do the following.
1. Place the address of the target register on the address bus input pins Addr[7:0].
2. While the P is placing this address value on the address bus, the address decoding circuitry should
assert the CS pin of the LIU, by toggling it "Low". This action enables communication between the P and
the LIU microprocessor interface block.
3. Next, the P should indicate that this current bus cycle is a Read operation by toggling the RD input pin
"Low". This action enables the bi-directional data bus output drivers of the LIU.
4. After the P toggles the Read signal "Low", the LIU will toggle the RDY output pin "Low". The LIU does this
to inform the P that the data is available to be read by the P, and that it is ready for the next command.
5. After the P detects the RDY signal and has read the data, it can terminate the Read Cycle by toggling the
RD input pin "High".
6. The CS input pin must be pulled "High" before a new command can be issued.
Write Cycle (For Pmode = "0" or "1")
Whenever a local P wishes to write a byte or word of data into a register within the LIU, it should do the follow-
ing.
1. Place the address of the target register on the address bus input pins Addr[7:0].
2. While the P is placing this address value on the address bus, the address decoding circuitry should
assert the CS pin of the LIU, by toggling it "Low". This action enables communication between the P and
the LIU microprocessor interface block.
3. The P should then place the byte or word that it intends to write into the target register, on the bi-direc-
tional data bus D[7:0].
4. Next, the P should indicate that this current bus cycle is a Write operation by toggling the WR input pin
"Low". This action enables the bi-directional data bus input drivers of the LIU.
5. After the P toggles the Write signal "Low", the LIU will toggle the RDY output pin "Low". The LIU does this
to inform the P that the data has been written into the internal register location, and that it is ready for the
next command.
6. The CS input pin must be pulled "High" before a new command can be issued.
FIGURE 35. ASYNCHRONOUS P INTERFACE SIGNALS DURING PROGRAMMED I/O READ AND WRITE OPERATIONS
CS
Addr[7:0]
D[7:0]
RD
WR
RDY
Valid Data for Readback
Data Available to Write Into the LIU
READ OPERATION
WRITE OPERATION
t
0
t
0
t
1
t
4
t
2
t
3
Valid Address
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| XRT73R12IB-F | 功能描述:外圍驅動器與原件 - PCI RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
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