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XRT73R12
48
REV. 1.0.3
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
TABLE 15: ASYNCHRONOUS TIMING SPECIFICATIONS
TABLE 16: SYNCHRONOUS TIMING SPECIFICATIONS
SYMBOL
PARAMETER
MIN
MAX
UNITS
t0
Valid Address to CS Falling Edge
0
-
ns
t1
CS Falling Edge to RD Assert
0
-
ns
t2
RD Assert to RDY Assert
-
65
ns
NA
RD Pulse Width (t2)
70
-
ns
t3
CS Falling Edge to WR Assert
0
-
ns
t4
WR Assert to RDY Assert
-
65
ns
NA
WR Pulse Width (t4)
70
-
ns
FIGURE 36. SYNCHRONOUS P INTERFACE SIGNALS DURING PROGRAMMED I/O READ AND WRITE OPERATIONS
SYMBOL
PARAMETER
MIN
MAX
UNITS
t0
Valid Address to CS Falling Edge
0
-
ns
t1
CS Falling Edge to RD Assert
0
-
ns
t2
RD Assert to RDY Assert
-
35
ns, see note 1
NA
RD Pulse Width (t2)
40
-
ns
t3
CS Falling Edge to WR Assert
0
-
ns
t4
WR Assert to RDY Assert
-
35
ns, see note 1
NA
WR Pulse Width (t4)
40
-
ns
PCLK Period
15
ns
PCLK Duty Cycle
PCLK "High/Low" time
CS
Addr[7:0]
D[7:0]
RD
WR
RDY
Valid Data for Readback
Data Available to Write Into the LIU
READ OPERATION
WRITE OPERATION
t
0
t
0
t
1
t
4
t
2
t
3
Valid Address
PCLK