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參數(shù)資料
| 型號： | XRT73R12IB |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 75/89頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC LIU E3/DS3/STS-1 12CH 420TBGA |
| 標準包裝： | 40 |
| 類型： | 線路接口裝置（LIU） |
| 驅動器/接收器數(shù)： | 12/12 |
| 規(guī)程： | DS3，E3，STS-1 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 420-LBGA 裸露焊盤 |
| 供應商設備封裝： | 420-TBGA（35x35） |
| 包裝： | 托盤 |
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XRT73R12
74
REV. 1.0.3
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
2
TAOS
R/W
Transmit All OneS Pattern - Channel_n:
This READ/WRITE bit-field is used to command the Transmit Section of
Channel_n to generate and transmit an unframed, All Ones pattern via the
DS3, E3 or STS-1 line signal (to the remote terminal equipment).
Whenever the user implements this configuration setting, the Transmit Sec-
tion will ignore the data that it is accepting from the System-side equipment
and output the "All Ones" Pattern.
0 - Configures the Transmit Section to transmit the data that it accepts from
the System-side Interface.
1 - Configures the Transmit Section to generate and transmit the Unframed,
All Ones pattern.
1
TxCLKINV
R/W
Transmit Clock Invert Select - Channel_n:
This READ/WRITE bit-field is used to select the edge of the TxCLK_n input
that the Transmit Section of Channel_n will use to sample the TxPOS_n and
TxNEG_n input pins, as described below.
0 - Configures the Transmit Section (within the corresponding channel) to
sample the TxPOS_n and TxNEG_n input pins upon the falling edge of
TxCLK_n.
1 - Configures the Transmit Section (within the corresponding channel) to
sample the TxPOS_n and TxNEG_n input pins upon the rising edge of
TxCLK_n.
NOTE: This is done on a per-channel basis.
0
TxLEV
R/W
Transmit Line Build-Out Select - Channel_n:
This READ/WRITE bit-field is used to enable or disable the Transmit Line
Build-Out (e.g., pulse-shaping) circuit within the corresponding channel.
The user should set this bit-field to either "0" or to "1" based upon the follow-
ing guidelines.
0 - If the cable length between the Transmit Output (of the corresponding
Channel) and the DSX-3/STSX-1 location is 225 feet or less.
1 - If the cable length between the Transmit Output (of the corresponding
Channel) and the DSX-3/STSX-1 location is more than 225 feet .
The user must follow these guidelines in order to insure that the Transmit
Section (of Channel_n) will always generate a DS3 pulse that complies with
the Isolated Pulse Template requirements per Bellcore GR-499-CORE, or
an STS-1 pulse that complies with the Pulse Template requirements per Tel-
cordia GR-253-CORE.
NOTE: This bit-field is ignored if the channel has been configured to operate
in the E3 Mode.
TABLE 35: TRANSMIT CONTROL REGISTER - CHANNEL N ADDRESS LOCATION = 0XM4
(N = [0:11] & M= 0-5 & 8-D)
BIT NUMBER
NAME
TYPE
DESCRIPTION
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相關代理商/技術參數(shù) |
參數(shù)描述 |
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| XRT73R12IB-F | 功能描述:外圍驅動器與原件 - PCI RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
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