參數(shù)資料
型號： XRT7302
廠商： Exar Corporation
英文描述： 2 Channel E3/DS3/STS-1 Line Interface Unit(2通道 E3/DS3/STS-1線接口單元)
中文描述： 2頻道E3/DS3/STS-1線路接口單元（2通道E3/DS3/STS-1線接口單元）
文件頁數(shù)： 9/62頁
文件大?。?/td> 715K
代理商： XRT7302
á
2 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
XRT7302
REV. 1.1.6
5
14
LCV0
O
Line Code Violation Indicator - Channel 0:
Whenever the Receive Section of Channel 0 detects a Line Code Violation, it
pulses this output pin "High". This output pin remains "Low" at all other times.
N
OTE
:
The XRT7302 outputs an NRZ pulse via this output pin. It is advisable
to sample this output pin via the RxClk0 clock output signal.
15
RLOL0
O
Receive Loss of Lock Output Indicator - Channel 0:
This output pin toggles "High" if Channel 0 of the XRT7302 has detected a
Loss of Lock Condition. Channel 0 declares an LOL (Loss of Lock) Condition
if the recovered clock frequency deviates from the Reference Clock frequency
(available at the EXClk(n) input pin) by more than 0.5%.
16
EXClk0
I
External Reference Clock Input - Channel 0:
Apply a 34.368 MHz clock signal for E3 applications, a 44.736 MHz clock sig-
nal for DS3 applications or a 51.84 MHz clock signal for SONET STS-1 appli-
cations.
N
OTES
:
1. It is permissible to use the same clock which is also driving the TxClk
input pin.
2. It is permissible to operate the two Channels at different data rates.
17
CS/(ENDECDIS)
I
Microprocessor Serial Interface - Chip Select Input/Encoder-Decoder
Disable Input:
This pin’s functionality depends on whether the XRT7302 is operating in the
HOST or Hardware Mode.
HOST Mode - Chip Select Input
The Local Microprocessor must assert this pin (set it to "0") in order to enable
communication with the XRT7302 via the Microprocessor Serial Interface.
N
OTE
:
This pin is internally pulled “High".
Hardware Mode - Encoder/Decoder Disable Input
Setting this input pin "High" disables the B3ZS/HDB3 Encoder & Decoder
blocks in the XRT7302 and configures it to transmit and receive the line signal
in an AMI format.
Setting this input pin "Low" enables the B3ZS/HDB3 Encoder & Decoder
blocks and configures it to transmit and receive the line signal in the B3ZS for-
mat for STS-1/DS3 operation or in the HDB3 format for E3 operation.
N
OTE
:
If the XRT7302 is operating in the Hardware Mode, this pin setting con-
figures the B3ZS/HDB3 Encoder and Decoder Blocks for both Channels.
18
SClk/(RxOFF1)
I
Microprocessor Serial Interface Clock Signal/Channel 1 Receiver Shut
OFF Input:
The function of this pin depends on whether the XRT7302 is operating in the
HOST Mode or in the Hardware Mode.
HOST Mode - Microprocessor Serial Interface Clock Signal:
This signal is used to sample the data on the SDI pin on the rising edge of this
signal. Additionally, during Read operations the Microprocessor Serial Inter-
face updates the SDO output on the falling edge of this signal.
Hardware Mode - Channel 1 Receiver Shut OFF input pin:
Setting this input pin "High" shuts off the Channel 1 receiver. Setting this input
pin "Low" enables the Receive Section for full operation.
PIN DESCRIPTION
P
IN
#
S
IGNAL
N
AME
T
YPE
D
ESCRIPTION
相關(guān)PDF資料
PDF描述
XRT73L02M TWO CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
XRT73L02MIV TWO CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
XRT73L02 2 Channel E3/DS3/STS-1 Line Interface Unit(2通道 E3/DS3/STS-1線接口單元)
XRT73L03A 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
XRT73L03AIV 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
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