參數(shù)資料
型號： XRT7302
廠商： Exar Corporation
英文描述： 2 Channel E3/DS3/STS-1 Line Interface Unit(2通道 E3/DS3/STS-1線接口單元)
中文描述： 2頻道E3/DS3/STS-1線路接口單元（2通道E3/DS3/STS-1線接口單元）
文件頁數(shù)： 51/62頁
文件大?。?/td> 715K
代理商： XRT7302
á
PRELIMINARY
2 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
XRT7302
REV. P1.1.6
47
4.3
T
HE
R
EMOTE
L
OOP
-B
ACK
M
ODE
When a given channel of the XRT7302 is configured
to operate in the Remote Loop-Back Mode, the chan-
nel ignores any signals that are input to the TPData
and TNData input pins. The channel receives the in-
coming line signal via the RTIP and RRing input pins.
This data is processed through the entire Receive
Section of the channel and outputs to the Receive
Terminal Equipment via the RPOS, RNEG and RxClk
output pins. Additionally, this data is internally looped
back into the Pulse-Shaping block in the Transmit
Section. At this point, this data is routed through the
remainder of the Transmit Section of the channel and
transmitted out onto the line via the TTIP(n) and
TRing(n) output pins.
Figure 29 illustrates the path the data takes in the
XRT7302 when the chip is configured to operate in
the Remote Loop-Back Mode.
To configure a channel to operate in the Remote
Loop-Back Mode employ either one of the following
two steps
a. Operating in the HOST Mode
To configure Channel (n), write a "1" into the RLB bit-
field and a "0" into the LLB bit-field in Command Reg-
ister CR4.
b. Operating in the Hardware Mode
To configure Channel(n), pull both the RLB input pin
to “High" and the LLB input pin to "Low".
4.4
T
X
OFF F
EATURES
The Transmit Section of each Channel in the
XRT7302 can be shut off. When this feature is in-
voked, the Transmit Section of the configured channel
is shut-off and the Transmit Output signals TTIP(n)
and TRing(n) are tri-stated. This feature is useful for
system redundancy conditions or during diagnostic
testing.
a. Operating in the Hardware Mode
Shut off the Channel(n) Transmit Driver by toggling
the TxOFF(n) input pin "High". Turn on the Transmit
Driver by toggling the TxOFF(n) input pin "Low".
b. Operating in the HOST Mode
F
IGURE
29. T
HE
R
EMOTE
L
OOP
-B
ACK
PATH
IN
A
GIVEN
XRT7302 C
HANNEL
AGC/
Equalizer
Peak
Detector
LOS Detector
Slicer
Clock
Recovery
Data
Recovery
Invert
Loop MUX
HDB3/
B3ZS
Decoder
LOSTHR(n)
SDI
SDO
SClk
CS
REGR
RTIP(n)
RRing(n)
REQEN(n)
RxClk(n)
RPOS(n)
RNEG(n)
LCV(n)
ENDECDIS
RLOS(n)
LLB(n)
RLB(n)
TAOS(n)
TPData(n)
TNData(n)
TxClk(n)
RLOL(n) EXClk(n)
Device
Monitor
MTIP(n)
MRing(n)
Transmit
Logic
Duty Cycle Adjust
TxLEV(n)
TxOFF(n)
DMO(n)
TTIP(n)
TRing(n)
Pulse
Shaping
HDB3/
B3ZS
Encoder
Serial
Processor
Interface
Remote
Loop-Back Path
Notes:
1. (n) = 0 or 1 for respective Channels
2. Serial Processor Interface input pins are shared by the two Channels in HOST Mode and redefined in Hardware Mode.
COMMAND REGISTER CR4-(n)
D4
D3
D2
D1
D0
X
STS-1/DS3_Ch(n) E3_Ch(n)
LLB(n)
RLB(n)
X
X
X
0
1
相關(guān)PDF資料
PDF描述
XRT73L02M TWO CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
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