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參數(shù)資料
| 型號： | XRT7302 |
| 廠商： | Exar Corporation |
| 英文描述： | 2 Channel E3/DS3/STS-1 Line Interface Unit(2通道 E3/DS3/STS-1線接口單元) |
| 中文描述： | 2頻道E3/DS3/STS-1線路接口單元（2通道E3/DS3/STS-1線接口單元） |
| 文件頁數(shù)： | 59/62頁 |
| 文件大?。?/td> | 715K |
| 代理商： | XRT7302 |
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PRELIMINARY
2 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
XRT7302
REV. P1.1.6
55
A4 and A5 must be set to "0" as shown in Figure 31.
Bit 8 - A6:
The value of "A6" is a don't care.
Once these first 8 bits have been written into the Mi-
croprocessor Serial Interface, the subsequent action
depends upon whether the current operation is a
Read or Write operation.
Read Operation
Once the last address bit (A3) has been clocked into
the SDI input, the Read operation proceeds through
an idle period lasting three SClk periods. On the fall-
ing edge of SClk Cycle #8 (see Figure 31) the serial
data output signal (SDO) becomes active. At this
point, reading the data contents of the addressed
Command Register at Address [A3, A2, A1, A0] via
the SDO output pin can begin. The Microprocessor
Serial Interface outputs this five bit data word (D0
through D4) in ascending order with the LSB first, on
the falling edges of the SClk pin. Consequently, the
data on the SDO output pin is sufficiently stable for
reading by the Microprocessor on the very next rising
edge of the SClk pin.
Write Operation
Once the last address bit (A3) has been clocked into
the SDI input, the Write operation proceeds through
an idle period lasting three SClk periods. Prior to the
rising edge of SClk Cycle # 9 (see Figure 31). Apply
the desired eight bit data word to the SDI input pin via
the Microprocessor Serial Interface. The Micropro-
cessor Serial Interface latches the value on the SDI
input pin on the rising edge of SClk. Apply this word
(D0 through D7) serially, in ascending order with the
LSB first.
Simplified Interface Option
The design of the circuitry connecting to the Micro-
processor Serial Interface can be simplified by tying
both the SDO and SDI pins together and reading data
from and/or writing data to this combined signal. This
simplification is possible because only one of these
signals are active at any given time. The inactive sig-
nal is tri-stated.
N
OTES
:
1. A4 and A5 is always "0"
2. R/W = "1" for "Read" Operations
3. R/W = "0" for "Write" Operations
4. Shaded blocks denotes a "don't care" value
F
IGURE
31. M
ICROPROCESSOR
S
ERIAL
I
NTERFACE
D
ATA
S
TRUCTURE
D0
D1
D2
0
0
0
D4
D3
High Z
SDO
A0
D0
R/W
D1
A6
0
0
A3
A2
A1
D7
D6
D5
D4
D3
D2
SDI
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
SClk
CS
High Z
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| XRT73L02M | TWO CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT |
| XRT73L02MIV | TWO CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT |
| XRT73L02 | 2 Channel E3/DS3/STS-1 Line Interface Unit(2通道 E3/DS3/STS-1線接口單元) |
| XRT73L03A | 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT |
| XRT73L03AIV | 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT |
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