參數(shù)資料
型號： XRT7302
廠商： Exar Corporation
英文描述： 2 Channel E3/DS3/STS-1 Line Interface Unit(2通道 E3/DS3/STS-1線接口單元)
中文描述： 2頻道E3/DS3/STS-1線路接口單元（2通道E3/DS3/STS-1線接口單元）
文件頁數(shù)： 49/62頁
文件大?。?/td> 715K
代理商： XRT7302
á
PRELIMINARY
2 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
XRT7302
REV. P1.1.6
45
4.0
DIAGNOSTIC FEATURES OF THE XRT7302
The XRT7302 supports equipment diagnostic activi-
ties by supporting the following Loop-Back modes in
each channel in the XRT7302:
Analog Local Loop-Back
Digital Local Loop-Back
Remote Loop-Back
4.1
T
HE
A
NALOG
L
OCAL
L
OOP
-B
ACK
M
ODE
When a given channel in the XRT7302 is configured
to operate in the Analog Local Loop-Back Mode, it ig-
nores any signals that are input to its RTIP(n) and
RRing(n) input pins. The Transmitting Terminal
Equipment transmits clock and data into this channel
via the TPData(n), TNData(n) and TxClk(n) input
pins. This data is processed through the Transmit
Clock Duty Cycle Adjust PLL and the HDB3/B3ZS
Encoder. Finally, this data outputs to the line via the
TTIP(n) and TRing(n) output pins. Additionally, this
data loops back into the Attenuator/Receive Equalizer
Block. This data is processed through the entire Re-
ceive Section of the channel. After this post-Loop-
Back data has been processed through the Receive
Section, it outputs to the Near-End Receiving Termi-
nal Equipment via the RPOS(n), RNEG(n) and Rx-
Clk(n) output pins.
Figure 27 illustrates the path the data takes in a given
channel of the XRT7302 when it is configured to op-
erate in the Analog Local Loop-Back Mode.
A given channel in the XRT7302 can be configured to
operate in the Analog Local Loop-Back Mode by em-
ploying either one of the following two steps:
N
OTE
:
See Table 2 for a description of Command Registers
and Addresses for the different channels.
a. Operating in the HOST Mode
To configure Channel (n) to operate in the Analog Lo-
cal Loop-Back Mode, write a "1" into the LLB(n) bit-
field and a "0" into the RLB(n) bit-field in Command
Register CR4.
COMMAND REGISTER CR4-(n)
b. Operating in the Hardware Mode
F
IGURE
27. A
CHANNEL
IN
THE
XRT7302
OPERATING
IN
THE
A
NALOG
L
OCAL
L
OOP
-B
ACK
M
ODE
EAGC/
Peak
Detector
LOS Detecto
Slicer
Clock
Recovery
Data
Recovery
Invert
Loop MUX
HDB3/
B3ZS
Decoder
LOSTHR(n)
SDI
SDO
SClk
CS
REGR
RTIP(n)
RRing(n)
REQEN(n)
RxClk(n)
RPOS(n)
RNEG(n)
LCV(n)
ENDECDIS
RLOS(n)
LLB(n)
RLB(n)
TAOS(n)
TPData(n)
TNData(n)
TxClk(n)
Notes:
1. (n) = 0 or 1 for respective Channels
2. Serial Processor Interface input pins are shared by the two Channels in HOST Mode and redefined in Hardware Mode.
RLOL(n) EXClk(n)
Device
Monitor
MTIP(n)
MRing(n)
Transmit
Logic
Duty Cycle Adjust
TxLEV(n)
TxOFF(n)
DMO(n)
TTIP(n)
TRing(n)
Pulse
Shaping
HDB3/
B3ZS
Encoder
Serial
Processor
Interface
Analog Local
Loop-Back Path
D4
D3
D2
D1
D0
X
STS-1/DS3_ Ch(n)
E3_ Ch(n)
LLB(n)
RLB(n)
X
X
X
1
0
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