XRT72L53
THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
REV. P1.1.6
á
PRELIMINARY
XII
T
ABLE
58: T
HE
R
ELATIONSHIP
BETWEEN
B
IT
4 (AMI/HDB3*)
WITHIN
THE
I/O C
ONTROL
R
EGISTER
AND
THE
B
I
-
POLAR
L
INE
C
ODE
THAT
IS
OUTPUT
BY
THE
T
RANSMIT
E3 LIU I
NTERFACE
B
LOCK
.................................... 300
II/O C
ONTROL
R
EGISTER
(A
DDRESS
= 0
X
01) ......................................................................................... 300
T
ABLE
59: T
HE
R
ELATIONSHIP
BETWEEN
THE
CONTENTS
OF
B
IT
2 (T
X
L
INE
C
LK
I
NV
)
WITHIN
THE
I/O C
ONTROL
R
EGISTER
AND
THE
T
X
L
INE
C
LK
CLOCK
EDGE
THAT
T
X
POS
AND
T
X
NEG
ARE
UPDATED
ON
..................... 300
Figure 125. Waveform/Timing Relationship between TxLineClk, TxPOS and TxNEG - TxPOS and TxNEG
are configured to be updated on the rising edge of TxLineClk ............................................................ 301
Figure 126. Waveform/Timing Relationship between TxLineClk, TxPOS and TxNEG - TxPOS and TxNEG
are configured to be updated on the falling edge of TxLineClk ........................................................... 301
5.2.6 Transmit Section Interrupt Processing .................................................................................................. 301
B
LOCK
I
NTERRUPT
E
NABLE
R
EGISTER
(A
DDRESS
= 0
X
04) ...................................................................... 302
T
X
E3 LAPD S
TATUS
AND
I
NTERRUPT
R
EGISTER
(A
DDRESS
= 0
X
34) ...................................................... 302
T
X
E3 LAPD S
TATUS
AND
I
NTERRUPT
R
EGISTER
(A
DDRESS
= 0
X
34) ...................................................... 303
5.3 T
HE
R
ECEIVE
S
ECTION
OF
THE
XRT72L53 (E3 M
ODE
O
PERATION
) .................................................................... 303
Figure 127. A Simple Illustration of the Receive Section of the XRT72L53 configured to operate in the E3
Mode .................................................................................................................................................... 303
5.3.1 The Receive E3 LIU Interface Block ...................................................................................................... 303
Figure 128. A Simple Illustration of the Receive E3 LIU Interface Block ............................................ 304
Figure 129. Behavior of the RxPOS, RxNEG and RxLineClk signals during data reception of Unipolar Data
305
I/O C
ONTROL
R
EGISTER
(A
DDRESS
= 0
X
01) .......................................................................................... 305
T
ABLE
60: T
HE
R
ELATIONSHIP
BETWEEN
THE
CONTENTS
OF
B
IT
2 (T
X
L
INE
C
LK
I
NV
)
WITHIN
THE
I/O C
ONTROL
R
EGISTER
AND
THE
T
X
L
INE
C
LK
CLOCK
EDGE
THAT
T
X
POS
AND
T
X
NEG
ARE
UPDATED
ON
..................... 305
Figure 130. Illustration on how a Channel of the Receive E3 Framer (within the XRT72L53 Framer IC) being
interface to theXRT73L03 Line Interface Unit, while operating in Bipolar Mode ................................. 306
Figure 131. Illustration of AMI Line Code ........................................................................................... 307
Figure 132. Illustration of two examples of HDB3 Decoding .............................................................. 307
II/O C
ONTROL
R
EGISTER
(A
DDRESS
= 0
X
01) ......................................................................................... 308
T
ABLE
61: T
HE
R
ELATIONSHIP
BETWEEN
THE
CONTENTS
OF
B
IT
1 (R
X
L
INE
C
LK
I
NV
)
OF
THE
I/O C
ONTROL
R
EG
-
ISTER
,
AND
THE
SAMPLING
EDGE
OF
THE
R
X
L
INE
C
LK
SIGNAL
................................................................... 308
Figure 133. Waveform/Timing Relationship between RxLineClk, RxPOS and RxNEG - When RxPOS and
RxNEG are to be sampled on the rising edge of RxLineClk ................................................................ 309
Figure 134. Waveform/Timing Relationship between RxLineClk, RxPOS and RxNEG - When RxPOS and
RxNEG are to be sampled on the falling edge of RxLineClk ............................................................... 309
5.3.2 The Receive E3 Framer Block ............................................................................................................... 309
Figure 135. A Simple Illustration of the Receive E3 Framer Block and the Associated Paths to the Other
Functional Blocks ................................................................................................................................ 310
Figure 136. The State Machine Diagram for the Receive E3 Framer E3 Frame Acquisition/Maintenance Al-
gorithm ................................................................................................................................................. 311
Figure 137. Illustration of the E3, ITU-T G.751 Framing Format ........................................................ 311
R
X
E3 I
NTERRUPT
S
TATUS
R
EGISTER
- 1 (A
DDRESS
= 0
X
14) .................................................................. 312
R
X
E3 C
ONFIGURATION
& S
TATUS
R
EGISTER
- 2 (A
DDRESS
= 0
X
11) ....................................................... 313
R
X
E3 I
NTERRUPT
S
TATUS
R
EGISTER
- 1 (A
DDRESS
= 0
X
14) .................................................................. 313
R
X
E3 I
NTERRUPT
S
TATUS
R
EGISTER
- 1 (A
DDRESS
= 0
X
14) .................................................................. 313
R
X
E3 C
ONFIGURATION
& S
TATUS
R
EGISTER
- 2 (A
DDRESS
= 0
X
11) ....................................................... 314
PMON F
RAMING
B
IT
/B
YTE
E
RROR
C
OUNT
R
EGISTER
- MSB (A
DDRESS
= 0
X
52) ................................... 314
PMON F
RAMING
B
IT
/B
YTE
E
RROR
C
OUNT
R
EGISTER
- LSB (A
DDRESS
= 0
X
53) .................................... 314
R
X
E3 C
ONFIGURATION
& S
TATUS
R
EGISTER
- 2 (A
DDRESS
= 0
X
11) ....................................................... 315
T
ABLE
62: T
HE
R
ELATIONSHIP
BETWEEN
THE
L
OGIC
S
TATE
OF
THE
R
X
OOF
AND
R
X
LOF
OUTPUT
PINS
,
AND
THE
F
RAMING
S
TATE
OF
THE
R
ECEIVE
E3 F
RAMER
BLOCK
............................................................................ 315
R
X
E3 C
ONFIGURATION
& S
TATUS
R
EGISTER
- 2 (A
DDRESS
= 0
X
11) ....................................................... 316
R
X
E3 I
NTERRUPT
S
TATUS
R
EGISTER
- 1 (A
DDRESS
= 0
X
14) .................................................................. 316
R
X
E3 C
ONFIGURATION
& S
TATUS
R
EGISTER
- 2 (A
DDRESS
= 0
X
11) ....................................................... 316
R
X
E3 I
NTERRUPT
S
TATUS
R
EGISTER
- 1 (A
DDRESS
= 0
X
14) .................................................................. 317
R
X
E3 C
ONFIGURATION
& S
TATUS
R
EGISTER
- 2 (A
DDRESS
= 0
X
11) ....................................................... 317