XRT72L50
SINGLE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
REV. P1.1.3
á
PRELIMINARY
IV
T
X
E3 TTB-8 R
EGISTER
(A
DDRESS
= 0
X
40) ........................................................................................... 102
T
X
E3 TTB-9 R
EGISTER
(A
DDRESS
= 0
X
41) ........................................................................................... 102
T
X
E3 TTB-10 R
EGISTER
(A
DDRESS
= 0
X
42) ......................................................................................... 103
T
X
E3 TTB-11 R
EGISTER
(A
DDRESS
= 0
X
43) ......................................................................................... 103
T
X
E3 TTB-12 R
EGISTER
(A
DDRESS
= 0
X
44) ......................................................................................... 103
T
X
E3 TTB-13 R
EGISTER
(A
DDRESS
= 0
X
45) ......................................................................................... 104
T
X
E3 TTB-14 R
EGISTER
(A
DDRESS
= 0
X
46) ......................................................................................... 104
T
X
E3 TTB-15 R
EGISTER
(A
DDRESS
= 0
X
47) ......................................................................................... 104
T
X
E3 FA1 E
RROR
M
ASK
R
EGISTER
(A
DDRESS
= 0
X
48) ......................................................................... 105
T
X
E3 FA2 E
RROR
M
ASK
R
EGISTER
(A
DDRESS
= 0
X
49) ......................................................................... 105
T
X
E3 BIP-8 E
RROR
M
ASK
R
EGISTER
(A
DDRESS
= 0
X
4A) ...................................................................... 105
2.3.7 Transmit E3 Framer Configuration Registers (ITU-T G.751) ................................................................. 106
T
X
E3 C
ONFIGURATION
R
EGISTER
(A
DDRESS
= 0
X
30) ............................................................................ 106
T
X
E3 LAPD C
ONFIGURATION
R
EGISTER
(A
DDRESS
= 0
X
33) .................................................................. 107
T
X
E3 LAPD S
TATUS
AND
I
NTERRUPT
R
EGISTER
(A
DDRESS
= 0
X
34) ...................................................... 108
T
X
E3 S
ERVICE
B
ITS
R
EGISTER
(A
DDRESS
= 0
X
35) ................................................................................ 109
T
X
E3 FAS E
RROR
M
ASK
R
EGISTER
- 0 (A
DDRESS
= 0
X
48) ................................................................... 109
T
X
E3 FAS E
RROR
M
ASK
R
EGISTER
- 1 (A
DDRESS
= 0
X
49) ................................................................... 109
T
X
E3 BIP-4 E
RROR
M
ASK
R
EGISTER
(A
DDRESS
= 0
X
4A) ...................................................................... 110
2.3.8 Performance Monitor Registers ............................................................................................................. 110
PMON LCV E
VENT
C
OUNT
R
EGISTER
- LSB (A
DDRESS
= 0
X
51) ........................................................... 110
PMON F
RAMING
B
IT
/B
YTE
E
RROR
C
OUNT
R
EGISTER
- MSB (A
DDRESS
= 0
X
52) ................................... 111
PMON F
RAMING
B
IT
/B
YTE
E
RROR
C
OUNT
R
EGISTER
- LSB (A
DDRESS
= 0
X
53) .................................... 111
PMON P
ARITY
E
RROR
C
OUNT
R
EGISTER
- MSB (A
DDRESS
= 0
X
54) ..................................................... 111
PMON P
ARITY
E
RROR
C
OUNT
R
EGISTER
- LSB (A
DDRESS
= 0
X
55) ...................................................... 111
PMON FEBE E
VENT
C
OUNT
R
EGISTER
DDRESS
= 0
X
56) ........................................................ 112
PMON FEBE E
VENT
C
OUNT
R
EGISTER
- LSB (A
DDRESS
= 0
X
57) ......................................................... 112
PMON CP-B
IT
E
RROR
C
OUNT
R
EGISTER
- MSB (A
DDRESS
= 0
X
58) ..................................................... 112
PMON CP-B
IT
E
RROR
C
OUNT
R
EGISTER
- LSB (A
DDRESS
= 0
X
59) ...................................................... 113
PMON H
OLDING
R
EGISTER
(A
DDRESS
= 0
X
6C) ..................................................................................... 113
O
NE
-S
ECOND
E
RROR
S
TATUS
R
EGISTER
(A
DDRESS
= 0
X
6D) ................................................................ 113
LCV - O
NE
-S
ECOND
A
CCUMULATOR
R
EGISTER
- MSB (A
DDRESS
= 0
X
6E) ............................................ 114
LCV - O
NE
-S
ECOND
A
CCUMULATOR
R
EGISTER
- LSB (A
DDRESS
= 0
X
6F) .............................................. 114
F
RAME
P
ARITY
E
RRORS
- O
NE
-S
ECOND
A
CCUMULATOR
R
EGISTER
- MSB (A
DDRESS
= 0
X
70) ................ 114
F
RAME
P
ARITY
E
RRORS
- O
NE
-S
ECOND
A
CCUMULATOR
R
EGISTER
- LSB (A
DDRESS
= 0
X
71) ................. 115
F
RAME
CP-B
IT
E
RRORS
- O
NE
-S
ECOND
A
CCUMULATOR
R
EGISTER
- MSB (A
DDRESS
= 0
X
72) ............... 115
F
RAME
P
ARITY
E
RRORS
- O
NE
-S
ECOND
A
CCUMULATOR
R
EGISTER
- LSB (A
DDRESS
= 0
X
73) ................. 115
L
INE
I
NTERFACE
D
RIVE
R
EGISTER
(A
DDRESS
= 0
X
80) ............................................................................ 116
L
INE
I
NTERFACE
S
CAN
R
EGISTER
(A
DDRESS
= 0
X
81) ............................................................................. 118
HDLC C
ONTROL
R
EGISTER
(A
DDRESS
= 0
X
82) ..................................................................................... 119
2.4 T
HE
L
OSS
OF
C
LOCK
E
NABLE
F
EATURE
............................................................................................................. 119
A
DDRESS
= 0
X
01, F
RAMER
I/O C
ONTROL
R
EGISTER
.............................................................................. 120
2.5 U
SING
THE
PMON H
OLDING
R
EGISTER
.............................................................................................................. 120
2.6 T
HE
I
NTERRUPT
S
TRUCTURE
WITHIN
THE
F
RAMER
M
ICROPROCESSOR
I
NTERFACE
S
ECTION
................................. 120
T
ABLE
5: L
IST
OF
ALL
OF
THE
P
OSSIBLE
C
ONDITIONS
THAT
CAN
G
ENERATE
I
NTERRUPTS
WITHIN
EACH
CHANNEL
OF
THE
XRT72L50 F
RAMER
D
EVICE
...................................................................................................... 121
T
ABLE
6: A L
ISTING
OF
THE
XRT72L50 F
RAMER
D
EVICE
I
NTERRUPT
B
LOCK
R
EGISTERS
(
FOR
DS3 A
PPLICA
-
TIONS
) ................................................................................................................................................... 121
T
ABLE
7: A L
ISTING
OF
THE
XRT72L50 F
RAMER
D
EVICE
I
NTERRUPT
B
LOCK
R
EGISTERS
(
FOR
E3, ITU-T G.832
A
PPLICATIONS
) ...................................................................................................................................... 121
T
ABLE
8: A L
ISTING
OF
THE
XRT72L50 F
RAMER
D
EVICE
I
NTERRUPT
B
LOCK
R
EGISTER
(
FOR
E3, ITU-T G.751
A
PPLICATIONS
) ...................................................................................................................................... 122
B
LOCK
I
NTERRUPT
S
TATUS
R
EGISTER
(A
DDRESS
= 0
X
05) ...................................................................... 122
B
LOCK
I
NTERRUPT
E
NABLE
R
EGISTER
(A
DDRESS
= 0
X
04) ...................................................................... 123
T
ABLE
9: I
NTERRUPT
S
ERVICE
R
OUTINE
G
UIDE
(
FOR
DS3 A
PPLICATIONS
) ............................................. 123