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XRT72L50
SINGLE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
PRELIMINARY
REV. P1.1.3
III
R
X
E3 GC B
YTE
R
EGISTER
(A
DDRESS
= 0
X
1B) ....................................................................................... 77
R
X
E3 TTB-0 R
EGISTER
(A
DDRESS
= 0
X
1C) ............................................................................................ 78
R
X
E3 TTB-1 R
EGISTER
(A
DDRESS
= 0
X
1D) ............................................................................................ 78
R
X
E3 TTB-2 R
EGISTER
(A
DDRESS
= 0
X
1E) ............................................................................................ 78
R
X
E3 TTB-3 R
EGISTER
(A
DDRESS
= 0
X
1F) ............................................................................................ 79
R
X
E3 TTB-4 R
EGISTER
(A
DDRESS
= 0
X
20) ............................................................................................ 79
R
X
E3 TTB-5 R
EGISTER
(A
DDRESS
= 0
X
21) ............................................................................................ 79
R
X
E3 TTB-6 R
EGISTER
(A
DDRESS
= 0
X
22) ............................................................................................ 79
R
X
E3 TTB-7 R
EGISTER
(A
DDRESS
= 0
X
23) ............................................................................................ 80
R
X
E3 TTB-8 R
EGISTER
(A
DDRESS
= 0
X
24) ............................................................................................ 80
R
X
E3 TTB-9 R
EGISTER
(A
DDRESS
= 0
X
25) ............................................................................................ 80
R
X
E3 TTB-10 R
EGISTER
(A
DDRESS
= 0
X
26) .......................................................................................... 81
R
X
E3 TTB-11 R
EGISTER
(A
DDRESS
= 0
X
27) .......................................................................................... 81
R
X
E3 TTB-12 R
EGISTER
(A
DDRESS
= 0
X
28) .......................................................................................... 81
R
X
E3 TTB-13 R
EGISTER
(A
DDRESS
= 0
X
29 ........................................................................................... 81
R
X
E3 TTB-14 R
EGISTER
(A
DDRESS
= 0
X
2A) .......................................................................................... 82
R
X
E3 TTB-15 R
EGISTER
(A
DDRESS
= 0
X
2B) .......................................................................................... 82
R
X
E3
SSM
R
EGISTER
(A
DDRESS
= 0
X
2B) ................................................................................................ 82
2.3.4 Receive E3 Framer Configuration Registers (ITU-T G.751) ................................................................... 83
R
X
E3 C
ONFIGURATION
& S
TATUS
R
EGISTER
- 1 G.751 (A
DDRESS
= 0
X
10) ............................................. 83
R
X
E3 C
ONFIGURATION
& S
TATUS
R
EGISTER
- 2 (A
DDRESS
= 0
X
11) ........................................................ 83
R
X
E3 I
NTERRUPT
E
NABLE
R
EGISTER
- 1 (A
DDRESS
= 0
X
12) ................................................................... 84
R
X
E3 I
NTERRUPT
E
NABLE
R
EGISTER
- 2 (A
DDRESS
= 0
X
13) ................................................................... 85
R
X
E3 I
NTERRUPT
S
TATUS
R
EGISTER
- 1 (A
DDRESS
= 0
X
14) ................................................................... 85
R
X
E3 I
NTERRUPT
S
TATUS
R
EGISTER
- 2 (A
DDRESS
= 0
X
15) ................................................................... 86
R
X
E3 LAPD C
ONTROL
R
EGISTER
(A
DDRESS
= 0
X
18) ............................................................................. 87
R
X
E3 LAPD S
TATUS
R
EGISTER
(A
DDRESS
= 0
X
19) ................................................................................ 87
R
X
E3 S
ERVICE
B
IT
R
EGISTER
(A
DDRESS
= 0
X
1A) ................................................................................... 88
2.3.5 Transmit DS3 Configuration Registers .................................................................................................... 88
T
RANSMIT
DS3 C
ONFIGURATION
R
EGISTER
(A
DDRESS
= 0
X
30) ............................................................... 89
T
RANSMIT
DS3 FEAC C
ONFIGURATION
& S
TATUS
R
EGISTER
(A
DDRESS
= 0
X
31) .................................... 90
T
X
DS3 FEAC R
EGIS
T
ER
(A
DDRESS
= 0
X
32) .......................................................................................... 91
T
X
DS3 LAPD C
ONFIGURATION
R
EGISTER
(A
DDRESS
= 0
X
33) ................................................................. 91
T
X
DS3 LAPD S
TATUS
AND
I
NTERRUPT
R
EGISTER
(A
DDRESS
= 0
X
34) ..................................................... 92
T
X
DS3 M-B
IT
M
ASK
R
EGISTER
(A
DDRESS
= 0
X
35) ................................................................................. 92
T
X
DS3 F-B
IT
M
ASK
R
EGISTER
- 1 (A
DDRESS
= 0
X
36) ............................................................................. 93
T
X
DS3 F-B
IT
M
ASK
R
EGISTER
- 2 (A
DDRESS
= 0
X
37) ............................................................................. 94
T
X
DS3 F-B
IT
M
ASK
R
EGISTER
- 3 (A
DDRESS
= 0
X
38) ............................................................................. 94
T
X
DS3 F-B
IT
M
ASK
R
EGISTER
- 4 (A
DDRESS
= 0
X
39) ............................................................................. 94
2.3.6 Transmit E3 (ITU-T G.832) Configuration Registers ............................................................................... 94
T
X
E3 C
ONFIGURATION
R
EGISTER
(A
DDRESS
= 0
X
30) .............................................................................. 95
T
X
E3 LAPD C
ONFIGURATION
R
EGISTER
(A
DDRESS
= 0
X
33) ................................................................... 96
T
X
E3 LAPD S
TATUS
AND
I
NTERRUPT
R
EGISTER
(A
DDRESS
= 0
X
34) ........................................................ 96
T
X
E3 GC B
YTE
R
EGISTER
(A
DDRESS
= 0
X
35) ........................................................................................ 97
T
X
E3 MA B
YTE
R
EGISTER
(A
DDRESS
= 0
X
36) ........................................................................................ 98
T
X
E3 MA B
YTE
R
EGISTER
(A
DDRESS
= 0
X
36) ........................................................................................ 98
T
X
E3 NR B
YTE
R
EGISTER
(A
DDRESS
= 0
X
37) ........................................................................................ 98
T
X
E3 TTB-0 R
EGISTER
(A
DDRESS
= 0
X
38) ............................................................................................. 99
T
X
E3 TTB-1 R
EGISTER
(A
DDRESS
= 0
X
39) ............................................................................................. 99
T
X
E3 TTB-2 R
EGISTER
(A
DDRESS
= 0
X
3A) ............................................................................................ 99
T
X
E3 TTB-3 R
EGISTER
(A
DDRESS
= 0
X
3B) .......................................................................................... 100
T
X
E3 TTB-4 R
EGISTER
(A
DDRESS
= 0
X
3C) .......................................................................................... 100
T
X
E3 TTB-5 R
EGISTER
(A
DDRESS
= 0
X
3D) .......................................................................................... 101
T
X
E3 TTB-6 R
EGISTER
(A
DDRESS
= 0
X
3E) .......................................................................................... 101
T
X
E3 TTB-7 R
EGISTER
(A
DDRESS
= 0
X
3F) .......................................................................................... 101