XRT72L50
SINGLE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
REV. P1.1.3
á
PRELIMINARY
5
25
NibbleIntf
I
Nibble Interface Select Input Pin:
This input pin allows the user to configure the Transmit Payload Data Input
Interface and the Receive Payload Data Output Interface to operate in either
the "Serial-Mode" or the "Nibble/Parallel-Mode".
Setting this input pin "high" configures the Transmit and Receive Terminal
Interfaces to operate in the "Nibble/Parallel-Mode". In this mode, the “Transmit
Payload Data Input Interface” block will accept the “outbound” payload data
(from the Terminal Equipment) in a “nibble-parallel” manner via the
“TxNib[3:0]” input pins. Further, the “Receive Payload Data Output Interface”
block will output the “inbound” payload data (to the Terminal Equipment) in a
“nibble-parallel” manner via the “RxNib[3:0]” output pin.
Setting this input pin "low" configures the Transmit and Receive Terminal
Interfaces to operate in the "Serial" Mode. In this mode, the “Transmit Payload
Data Input Interface” block will accept the “outbound” payload data (from the
Terminal Equipment) in a “serial” manner via the “TxSer” input pin. Further,
the “Receive Payload Data Output Interface” block will output the “inbound”
payload data (to the Terminal Equipment) in a “serial” manner via the “RxSer”
output pin.
26
GND
****
Ground
27
MOTO
I
Motorola/Intel Processor Interface Select Mode:
This input pin allows the user to configure the Microprocessor Interface to
interface with either a "Motorola-type" or "Intel-type" microprocessor/micro-
controller. Tying this input pin to VCC, configures the microprocessor interface
to operate in the Motorola mode (e.g., the Framer device can be readily inter-
faced to a "Motorola type" local microprocessor). Tying this input pin to GND
configures the Microprocessor Interface to operate in the Intel Mode (e.g., the
Framer device can be readily interfaced to a “Intel type" local microproces-
sor).
28
Reset
I
Reset Input:
When this "active-low" signal is asserted, the Framer device will be asynchro-
nously reset. Additionally, all outputs will be "tri-stated", and all on-chip regis-
ters will be reset to their default values.
29
TestMode
***
Factory Test Pin:
The user should tie this pin to Ground.
30
VDD
****
Power Supply 3.3V + 5%
31
GND
****
Ground
32
D(0)
I/O
Bit 6 of Bi-Directional Data Bus (Microprocessor Interface Section):
See description of pin 39 D(7)
33
D(1)
I/O
Bit 6 of Bi-Directional Data Bus (Microprocessor Interface Section):
See description of pin 39 D(7)
34
D(2)
I/O
Bit 6 of Bi-Directional Data Bus (Microprocessor Interface Section):
See description of pin 39 D(7)
35
D(3)
I/O
Bit 6 of Bi-Directional Data Bus (Microprocessor Interface Section):
See description of pin 39 D(7)
PIN DESCRIPTION
P
IN
#
P
IN
N
AME
T
YPE
D
ESCRIPTION