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參數(shù)資料
| 型號： | XRT71D04 |
| 廠商： | Exar Corporation |
| 英文描述： | 4-Channel E3/DS3/STS-1 Jitter Attenuator,STS-1 to DS3 Desynchronizer(達(dá)到E3/DS3/STS-1振蕩要求的4通道振蕩衰減器) |
| 中文描述： | 4通道E3/DS3/STS-1抖動衰減器，STS - 1的到DS3 Desynchronizer（達(dá)到E3/DS3/STS-1振蕩要求的4通道振蕩衰減器） |
| 文件頁數(shù)： | 5/21頁 |
| 文件大小： | 223K |
| 代理商： | XRT71D04 |
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XRT71D04
4 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR, STS-1 TO DS3 DESYNCHRONIZER
PRELIMINARY
REV. P1.0.2
4
11
VDD
****
Digital Power Supply = 5V±5% or 3.3V±5%
12
MODE_CTRL
I
Mode Control:
When “High” in Multimode, all channels are independent. When “Low”, the
Master Channel (channel0) controls DS3/E3_chn, STS1_chn, RCLKES, FSS
and MCLKn. DJA is NOT affected.
Internal 50 K Ohm pull-up resistor.
13
ICT
I
In Circuit Testing Input.
(Active low):
With this pin tied to ground, all output pins will be in high impedance mode for
in-circuit-testing.
For normal operation this input pin should be tied to VDD.
Internal 50 K Ohm pull-up resistor.
14
HOST
I
Host/Hardware Mode Select:
An active-high input enables the Host mode. Data is written to the command
registers to configure the XRT71D04.
In the Host mode, the states of discrete input pins are inactive.
An active-low input enables the Hardware Mode.In this mode, the discrete
inputs are active.
Internal 50 K Ohm pull-down resistor.
15
FLRST
I
FIFO Limit Reset
Hardware Mode
Whenever the FIFO is within 2 bits of either underflow or overflow, the FL(n) will
be set high.
This pin allows the user to reset the state of FL(n), (FIFO Limit) output pin.
This pin when pulsed “High”, resets the the FL(n) output pin, (toggles to GND).
N
OTE
:
The FL(n) could be set “High” again if the FIFO is within 2 bits of either
underflow or overflow.
Host Mode
Reading the FL(n) bits in the status registers clears this FL(n) pin. Master
RESET also clears the FL(n) output.
This pin is tied to GND. FLRST has no effect in this mode.
Internal 50 K Ohm pull-down resistor.
16
RRNEG3
O
Received Recovered Negative Data (De-Jittered) Output - channel
3:
See description of pin 6
17
RRPOS3
Received Positive Data (De-Jittered) Output - channel 3:
See description of pin 5
18
RRCLK3
O
Received Recovered Output (De-jittered) Clock - channel 3:
See description of pin 4
19
VSS
O
Digital Ground
20
AVDD
****
Analog Power Supply = 5V±5% or 3.3V±5%
21
AVSS
****
Analog Ground
22
FL0
O
FIFO Limit - channel 0:
This output pin is driven high whenever the internal FIFO comes within two-bits
of being either underflow or overflow.
PIN DESCRIPTION
P
IN
#
N
AME
T
YPE
D
ESCRIPTION
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| XRT71D04ES | 功能描述:時鐘合成器/抖動清除器 4CH T3/E3 JA w/T73LC04A RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| XRT71D04IV | 功能描述:時鐘合成器/抖動清除器 4CH E3/DS3/STS1 JIT ATTEN DE-SYNCH RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| XRT71D04IVTR | 功能描述:時鐘合成器/抖動清除器 4CH E3/DS3/STS1 JIT ATTEN DE-SYNCH RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| XRT7250 | 制造商:EXAR 制造商全稱:EXAR 功能描述:DS3/E3 FRAMER IC |
| XRT7250ES-PCI | 功能描述:界面開發(fā)工具 Evaluation Board for XRT7250 Series RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V |
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