參數(shù)資料
型號(hào)： XRT71D04
廠商： Exar Corporation
英文描述： 4-Channel E3/DS3/STS-1 Jitter Attenuator,STS-1 to DS3 Desynchronizer(達(dá)到E3/DS3/STS-1振蕩要求的4通道振蕩衰減器)
中文描述： 4通道E3/DS3/STS-1抖動(dòng)衰減器，STS - 1的到DS3 Desynchronizer（達(dá)到E3/DS3/STS-1振蕩要求的4通道振蕩衰減器）
文件頁(yè)數(shù)： 15/21頁(yè)
文件大?。?/td> 223K
代理商： XRT71D04
á
XRT71D04
4 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR, STS-1 TO DS3 DESYNCHRONIZER
PRELIMINARY
REV. P1.0.2
14
The serial interface for the XRT71D04 and the
XRT7300 family of E3/DS3/STS-1 LIU’s, which
makes it easy to configure both the XRT71D04 and
the LIU with a single CS, SDI, SDO and SClk input
and output pins.
S
ERIAL
I
NTERFACE
O
PERATION
.
Serial interface data structure and timings are provid-
ed in Figure 5 and 6 respectively.
The clock signal is provided to the SClk and the CS is
asserted for 50 ns prior to the first rising edge of the
SClk.
B
IT
1—R/W (R
EAD
/W
RITE
) B
IT
This bit will be clocked into the SDI input, on the first
rising edge of SClk (after CS has been asserted).
This bit indicates whether the current operation is a
Read or Write operation. A “1” in this bit specifies a
Read operation; whereas, a “0” in this bit specifies a
Write operation.
Bits 2 through 5: The five (5) bit Address Values (la-
beled A0, A1, A2 ,A3,and A4)
The next four rising edges of the SClk signal will clock
in the 5-bit address value for this particular Read (or
Write) operation. The address selects the Command
Register for reading data from, or writing data to. The
address bits to the SDI input pin is applied in ascend-
ing order with the LSB (least significant bit) first.
B
IT
7:
A5 must be set to “0”, as shown in Figure 7.
B
IT
8—A6
The value of A6 is a don’t care.
Once these first 8 bits have been written into the Seri-
al Interface, the subsequent action depends upon
whether the current operation is a Read or Write op-
eration.
R
EAD
O
PERATION
Once the last address bit (A4) has been clocked into
the SDI input, the Read operation will proceed
through an idle period, lasting three SClk periods. On
the falling edge of SClk Cycle #8 (see Figure 7) the
serial data output signal (SDO) becomes active. At
this point the user can begin reading the data con-
tents of the addressed Command Register (at Ad-
dress [A4,A3, A2, A1, A0]) via the SDO output pin.
The Serial Interface will output this seven bit data
word (D0 through D6) in ascending order (with the
LSB first), on the falling edges of the SClk . The data
(on the SDO output pin) is stable for reading on the
very next rising edge of the SClk .
W
RITE
O
PERATION
Once the last address bit (A4) has been clocked into
the SDI input, the Write operation will proceed
through an idle period, lasting three SClk periods. Pri-
or to the rising edge of SClk Cycle #9 , eight bit data
word is applied to SDI input. Data on SDI is latched
on the rising edge of SClk.
T
ABLE
2: A
DDRESS
AND
B
IT
F
ORMATS
OF
THE
C
OMMAND
R
EGISTERS
A
DDR
C
OMMAND
R
EGISTER
T
YPE
D6
D5
D4
D3
D2
D1
D0
0X06
CR6
R/W
***
***
DS3/E3_ch0
DJA0
STS-1_ch0
ClkES0
FSS0
0x07
CR7
RO
***
***
***
***
***
***
FL0
0x0E
CR14
R/W
***
***
DS3/E3_ch1
DJA1
STS-1_ch1
ClkES1
FSS1
0x0F
CR15
RO
***
***
***
***
***
***
FL1
0x16
CR22
R/W
***
***
DS3/E3_ch2
DJA2
STS-1_ch2
ClkES2
FSS2
0x17
CR23
RO
***
***
***
***
***
***
FL2
0x1E
CR30
R/W
***
***
DS3/E3_ch3
DJA3
STS-1_ch3 CLKES3
FSS3
0x1F
CR31
RO
***
***
***
***
***
***
FL3
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