參數(shù)資料
型號(hào)： XRT4500
廠商： Exar Corporation
英文描述： MULTIPROTOCOL SERIAL NETWORK INTERFACE IC
中文描述： 多協(xié)議串行網(wǎng)絡(luò)接口芯片
文件頁(yè)數(shù)： 7/99頁(yè)
文件大小： 1384K
代理商： XRT4500
XRT4500
MULTIPROTOCOL SERIAL NETWORK INTERFACE IC
REV. 1.0.7
á
4
PIN DESCRIPTIONS
PIN
#
Signal
DTE
MODE
DCE
MODE
TYPE
FUNCTION
1
RX1D
D_RXD
D_TXD
O
Receiver 1 Digital Output – Digital Data Output to terminal
equipment
This output pin is the digital (TTL/CMOS level) representation of
the line signal that has been received via the RX1A (pin 78) and
RX1B (pin 79) input pins.
The exact role that this pin plays depends upon whether the
XRT4500 is operating in the DCE or DTE Mode.
DCE Mode – TXD Digital Output Signal
This output pin functions as the TXD Digital Output signal (which
should be input to the Terminal Equipment).
DTE Mode – RXD Digital Output Signal
This output pin functions as the RXD Digital Output signal (which
should be input to the Terminal Equipment).
2
VDD
Analog VDD
for Receiver 1, 2, 3
3
GND
I
Analog GND
for Receiver 1, 2, 3 and Transmitter 3
4
M0
I
Mode Control – Mode Select Input 0
This input pin, along with M1 and M2 are used to configure the
XRT4500 to operate in the desired “Communication Interface”
Mode. Table 3 and Table 4 present the relationship between
the states of the M2, M1 and M0 input pins and the correspond-
ing communication interface modes selected.
This input pin (along with M1 and M2) is internally latched into
the XRT4500, upon the rising edge of the “LATCH” signal. At this
point, changes in this input pin will not effect the “internally
latched” state of this pin.
This input pin contains an Internal 20K
pull-up to VDD.
5
M1
I
Mode Control – Mode Select Input 1
This input pin, along with M0 and M2 are used to configure the
XRT4500 to operate in the desired “Communication Interface”
Mode. Table 3 and Table 4 present the relationship between the
states of the M2, M1 and M0 input pins and the corresponding
communication interface modes selected.
This input pin (along with M0 and M2) is internally latched into the
XRT4500 device, upon the rising edge of the “LATCH” signal. At
this point, changes in this input pin will not effect the “internally
latched” state of this pin.
This input pin contains an Internal 20K
pull-up to VDD.
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