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參數(shù)資料
| 型號： | XRT4500 |
| 廠商： | Exar Corporation |
| 英文描述： | MULTIPROTOCOL SERIAL NETWORK INTERFACE IC |
| 中文描述： | 多協(xié)議串行網(wǎng)絡(luò)接口芯片 |
| 文件頁數(shù)： | 18/99頁 |
| 文件大?。?/td> | 1384K |
| 代理商： | XRT4500 |
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á
XRT4500
MULTIPROTOCOL SERIAL NETWORK INTERFACE IC
REV. 1.0.7
15
PIN DESCRIPTIONS (CONT.)
N
OTE
:
Signal names beginning with D_ are digital signals.
N
OTE
:
Signal names ending with B and A are the positive
and negative polarities of differential signals respectively.
PIN
#
Signal
DTE
MODE
DCE
MODE
TYPE FUNCTION
39
SLEW_CNTL
O
V.28/V.10 Slew-Rate Control Pin
– This pin permits the user to
specify the slew rate of the V.10 or V.28 output driver. The user
accompanies this by connecting a resistor (of a specific value)
between this pin and ground.
Figure 34 presents a plot which depicts the relationship
between the ‘Rise/Fall Time’ of a V.10 output signal (from the
XRT4500) and the value of this resistor.
Figure 35 presents a plot which depicts the relationship
between the slew-rate (expressed in terms of V/μs) of a V.28 out-
put signal (from the XRT4500) and the value of this resistor.
40
RX4D
D_CTS
D_RTS
O
Receiver 4 – Digital Data Output to Terminal Equipment
This output pin is the digital (CMOS level) representation of the
line signal that is applied to the RX4A (pin 37) and RX4B (pin 38)
input pins.
The exact role that this pin plays depends upon whether the
XRT4500 is operating in the DCE or DTE Mode.
DCE Mode – CTS (Clear to Send) Output Signal
For DCE Mode applications, this output pin should be connected
to the “CTS” input pin of the Terminal Equipment.
DTE Mode – RTS (Request to Send) Output Signal
For DTE Mode applications, this output pin should be connected
to the “RTS” input pin of the Terminal Equipment.
41
Vsense
I
Switching Regulator –
Voltage sense input
42
Isense
I
Switching Regulator –
Current sense input
43
GND_REG
Switching Regulator Ground
44
LATCH
I
Mode Control Input Latch Enable – Logic 0:
This input pin permits the user to latch the states of the Mode
Control Input pins (4, 5, and 6) (M0, M1, and M2) into the
XRT4500 circuitry. This feature frees up the signals (driving the
Mode Control Input pins) for other purposes.
Driving this input, from “l(fā)ow” to “high” latches the contents of the
Mode Control pins of the XRT4500 (into the XRT4500 circuitry).
For the duration that the LATCH input pin is “high”, the user can
change the state of the signals controller the M0, M1 and M2
input pins, without effecting the operation of the XRT4500.
45
CLKFS
O
Internally Generated 500kHz Clock –
This clock signal is inter-
nally used to drive both the switching regulator and the digital
‘Glitch’ filters. The user is advised to leave this pin floating.
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