參數(shù)資料
型號: XRT4500
廠商: Exar Corporation
英文描述: MULTIPROTOCOL SERIAL NETWORK INTERFACE IC
中文描述: 多協(xié)議串行網(wǎng)絡(luò)接口芯片
文件頁數(shù): 19/99頁
文件大?。?/td> 1384K
代理商: XRT4500
XRT4500
MULTIPROTOCOL SERIAL NETWORK INTERFACE IC
REV. 1.0.7
á
16
PIN DESCRIPTIONS (CONT.)
N
OTE
:
Signal names beginning with D_ are digital signals.
N
OTE
:
Signal names ending with B and A are the positive
and negative polarities of differential signals respectively
PIN
#
Signal
DTE
MODE
DCE
MODE
TYPE
FUNCTION
46
E_232H
I
High Speed RS-232 Enable –
Logic 0 enables high speed RS-
232 mode (drives 3K
in parallel with 1000pF at 256 KHz).
Internal 20K
pull-up to VDD.
This input pin permits the user to either enable or disable the
‘High-Speed RS-232 Driver’ feature. The non high speed mode
provides a 120 Kbps clock rate.
Note:
This pin setting applies to all ‘RS-232/V28 Drivers’ within
the XRT4500.
47
V
DD
Analog VDD for the Internal Switching Regulator
48
EN_OUT
I
Output Enable Pin for Receiver 5 and 8
This active-low output pin permits the user to tri-state the
“RX5D” and “RX8D” output pins (Pins 23 & 33).
Setting this input pin “l(fā)ow” causes the XRT4500 to tri-state the
“RX5D” and “RX8D” output pins. Conversely, setting this input
pin “high” enables the “RX5D” and the “RX8D” output drivers for
signal transmission to the local Terminal Equipment.
This input pin contains an internal 20k
pull-down resistor to
ground.
49
REG_CLK
I
Register Mode Clock Input Signal:
If the XRT4500 has been configured to operate in the “Regis-
tered” Mode, then a rising clock edge at this input causes the
XRT4500 to do the following.
Data at the TX5D and TX8D input pins (Pins 15 & 17) will be
latched into the XRT4500 circuitry.
Data will be outputted via the RX5D and RX8D pins (Pins 23
& 33).
This input pin has no function when the XRT4500 is operating in
the “Non-Registered” Mode. The user configures the XRT4500
to operate in the “Registered” Mode, by pulling the “REG” input
pin to V
DD
.
This input pin contains an internal 20k
pull-up to V
DD
.
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