參數(shù)資料
型號(hào)： XR88C681P/40
廠商： Exar Corporation
文件頁(yè)數(shù)： 46/101頁(yè)
文件大?。?/td> 0K
描述： IC UART CMOS DUAL 40PDIP
產(chǎn)品變化通告： Leaded UART, V&I Obsolescence 11/Apr/2011
標(biāo)準(zhǔn)包裝： 9
特點(diǎn)： *
通道數(shù)： 2，DUART
FIFO's： 1 字節(jié)，3 字節(jié)
電源電壓： 4.75 V ~ 5.25 V
帶并行端口： 是
帶CMOS： 是
安裝類型： 通孔
封裝/外殼： 40-DIP（0.600"，15.24mm）
供應(yīng)商設(shè)備封裝： 40-PDIP
包裝： 管件
XR88C681
49
Rev. 2.11
-S0
-S1
-S2
MN/-MX
-S0
-S1
-S2
CLK
DEN
DT/-R
ALE
-INTA
-MRDC
-MWTC
-IORC
-IOWC
8288 Bus Controller
74LS373
C
-MEMR
-MEMW
-IOR
-IOW
AD0 - AD7
AD8 - AD15
INTR
CLK
D0 - D7
D8 - D15
A0 - A7
A8 - A15
D
Q
D
Q
8086 CPU
Figure 22. Schematic of the 8086 CPU Mode (Max Mode)
8086 C Interrupt Processing
If a peripheral component requires interrupt service from
the CPU, it will assert the CPU’s INTR input (by toggling it
high).
Once the CPU has completed its current
instruction, it will assert the -INTA pin (if operating in the
“min” mode) or set the -S0, -S1, and -S2 pins to “0” (see
Table 15). In either case, the -IACK input of the peripheral
will be asserted. Once this happens, the interrupting
peripheral is expected to place an “interrupt vector” byte
on D0 - D7 of the data bus. The 8086 P will read this data
and multiply this value by the number 4 in order to
determine the location of the interrupt service routine in
memory. Since this “interrupt vector” is 8 bits wide, the
8086 P can accommodate up to 256 different interrupt
vectors (0 - 255). Additionally, since each vector is
multiplied by “4”, the user is expected to reserve the first
1K byte of memory for the Interrupt Service
Routines/Jump Table.
Figure 23 presents a schematic of the XR88C681
DUART interfacing to a “min” Mode 8086 CPU device.
Please note that the DUART has been configured to
operate in the Z-Mode. Therefore, the user must account
for the IEI input to the DUART device.
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