參數(shù)資料
型號(hào)： XR88C681P/40
廠商： Exar Corporation
文件頁(yè)數(shù)： 38/101頁(yè)
文件大?。?/td> 0K
描述： IC UART CMOS DUAL 40PDIP
產(chǎn)品變化通告： Leaded UART, V&I Obsolescence 11/Apr/2011
標(biāo)準(zhǔn)包裝： 9
特點(diǎn)： *
通道數(shù)： 2，DUART
FIFO's： 1 字節(jié)，3 字節(jié)
電源電壓： 4.75 V ~ 5.25 V
帶并行端口： 是
帶CMOS： 是
安裝類型： 通孔
封裝/外殼： 40-DIP（0.600"，15.24mm）
供應(yīng)商設(shè)備封裝： 40-PDIP
包裝： 管件
XR88C681
41
Rev. 2.11
from issuing any interrupt requests to the CPU. This
“l(fā)ower priority” DUART will be prohibited from issuing
interrupts until the IEO pin of the “highest priority” DUART
has toggled “high”.
Referring, once again, to
Figure 15, the further to the right
a DUART device is, the lower its interrupt priority. The
right most DUART has the lowest-interrupt priority
because its “interrupt request” capability can be disabled
by the actions of any one of the DUARTs to the left.
Figure 16 presents a timing diagram depicting the
sequence of events that will occur during and following an
Interrupt Request from the DUART.
-INTR
-IACK
-RD
D0 - D7
FLOAT
NOT VALID
VECTOR
FLOAT
IEI
IEO
Reset IUS
Command
Figure 16. Timing Diagram Illustrating the Sequence of Events Occurring Between the
DUART and the CPU During an Interrupt Request/Acknowledge and Servicing
Additional Things to Note About Z-Mode Operation
Z-Mode operation is supported by all Zilog Peripheral
components. All Zilog Peripheral components have an
Interrupt Vector Register, Interrupt Acknowledge (IACK)
input, IEI input, and an IEO output. Therefore,
Figure 15
could have easily included some other peripheral
components, in addition to or in lieu of DUARTs.
As mentioned earlier, Z-Mode operation is recommended
if the DUART is to be interfaced to the following
processors.
D
Z-80 Microprocessor (Interrupt Mode 2)
D
8088 C
D
8086 P
D
80286 - 80586 P
Please note that it is possible to interface the 80X86
Family of microprocessors to an I-Mode DUART,
however, additional components and design complexity
would be required in order to accomplish this. The
technique/approaches to interfacing the Z-Mode DUART
to these microprocessors is presented in detail, in the
following sections.
C.6.2.1 Z-80 Microprocessor
The Z-80 P consists of an 8 bit Data Bus, a 16 bit Address
Bus and numerous control pins. The Z-80 P is a very
flexible processor which can actually interface to either a
Z-Mode or an I-Mode DUART device. This is because the
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