參數(shù)資料
型號(hào)： XR88C681P/40
廠商： Exar Corporation
文件頁(yè)數(shù)： 11/101頁(yè)
文件大小： 0K
描述： IC UART CMOS DUAL 40PDIP
產(chǎn)品變化通告： Leaded UART, V&I Obsolescence 11/Apr/2011
標(biāo)準(zhǔn)包裝： 9
特點(diǎn)： *
通道數(shù)： 2，DUART
FIFO's： 1 字節(jié)，3 字節(jié)
電源電壓： 4.75 V ~ 5.25 V
帶并行端口： 是
帶CMOS： 是
安裝類型： 通孔
封裝/外殼： 40-DIP（0.600"，15.24mm）
供應(yīng)商設(shè)備封裝： 40-PDIP
包裝： 管件
XR88C681
17
Rev. 2.11
Bit 7
Bit 6
Bit 5
Bit 4
Description
0
1
0
Reset Error Status.
Clears the Received Break
(RB), Parity Error (PE), Framing Error (FE) and
Overrun Error (OE) status bits, SR[7:3].
Specifically, if the Error Mode, for a particular chan-
nel is set at “Block” Error Mode, this command will
reset all of the Receiver Error Indicators in the Status
Register. In the Block Error Mode, once either a PE,
FE, OE, or RB occurs, the error will continue to be
flagged in the Status Register, until this command is
issued.
If the Error Mode, for a particular channel is set to
“Character Error Mode”, then the contents of the
Status Register for PE, FE, and RB are reflected on
a character by character basis. In the “Character
Error Mode”, the state of these indicators is based
only upon the character that is at the top of the RHR.
The OE indicator is always presented as a “Block
Error Mode” indicator, and requires this command to
be reset.
0
1
0
1
Reset Break Change Interrupt.
Clears the chan-
nel’s break change interrupt status bit.
0
1
0
Start Break.
Forces the TXDn output low. The
transmitter must be enabled to start a break. If the
transmitter is empty, the start of the break may be
delayed up to two bit times. If the transmitter is ac-
tive, the break begins when the transmission of
those characters in the THR is completed, viz.,
TXEMP must be true before the break will begin.
0
1
Stop Break.
The TXDn line will go high within two
bit times. TXDn will remain high for one bit time be-
fore the next character, if any, is transmitted.
1
0
Set Rx BRG Select Extend Bit.
Sets the channel’s
“Receiver BRG Select Extend Bit” to 1.
1
0
1
Clear Rx BRG Select Extend Bit.
Clears the chan-
nel’s “Receiver BRG Select Extend Bit” to 0.
1
0
1
0
Set Tx BRG Select Extend Bit.
Sets the channel’s
“Transmitter BRG Select Extend Bit” to 1.
1
0
1
Clear Tx BRG Select Extend Bit.
Clears the chan-
nel’s “Transmitter BRG Select Extend Bit” to 0.
Table 3. Miscellaneous Commands, Upper Nibble of all Command Registers,
Unless Otherwise Specified (Cont’d)
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