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參數(shù)資料
| 型號： | XR20V2172IL64-F |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 7/51頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC UART/TXRX I2C/SPI RS232 64QFN |
| 標(biāo)準(zhǔn)包裝： | 260 |
| 特點(diǎn)： | * |
| 通道數(shù)： | 2，DUART |
| FIFO's： | 64 字節(jié) |
| 規(guī)程： | RS232 |
| 電源電壓： | 2.97 V ~ 3.63 V |
| 帶自動(dòng)流量控制功能： | 是 |
| 帶IrDA 編碼器/解碼器： | 是 |
| 帶故障啟動(dòng)位檢測功能： | 是 |
| 帶調(diào)制解調(diào)器控制功能： | 是 |
| 帶CMOS： | 是 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 64-QFN（9x9） |
| 包裝： | 托盤 |
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FIGURE 11. RECEIVER OPERATION IN FIFO AND AUTO RTS FLOW CONTROL MODE
Receive Data Shift
Register (RSR)
RXFIFO1
16X or 8X or 4X Clock
( DLD[5:4] )
Error
Ta
gs
(64
-s
et
s)
Err
or
Tag
sin
LS
R
b
its
4:
2
Receive Data Characters
FIFO
Trigger=16
Example
: - RX FIFO trigger level selected at 16 bytes
(See Note Below)
Data fills to
Halt Level
Data falls to
Resume Level
Data Bit
Validation
Receive
Data FIFO
Receive
Data
Receive Data
Byte and Errors
RHR Interrupt (ISR bit-2) programmed for
desired FIFO trigger level.
FIFO is Enabled by FCR bit-0=1
RTS# de-asserts when data fills to the Halt Level
to suspend remote transmitter.
Enable by EFR bit-6=1, MCR bit-1.
RTS# re-asserts when data falls to the Resume
Level to restart remote transmitter.
Enable by EFR bit-6=1, MCR bit-1.
64 bytes by 11-bit wide
FIFO
XR20V2172
15
REV. 1.0.2
TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER
2.10
Auto RTS (Hardware) Flow Control
Automatic RTS hardware flow control is used to prevent data overrun to the local receiver FIFO. The RTS#
output is used to request remote unit to suspend/resume data transmission. The auto RTS flow control
features is enabled to fit specific application requirement (see Figure 12):
Enable auto RTS flow control using EFR bit-6.
The auto RTS function must be started by asserting RTS# output pin (MCR bit-1 to logic 1 after it is enabled).
If using the Auto RTS interrupt:
Enable RTS interrupt through IER bit-6 (after setting EFR bit-4). The UART issues an interrupt when the
RTS# pin makes a transition from low to high: ISR bit-5 will be set to logic 1.
2.11
Auto RTS Halt and Resume
The RTS# pin will not be forced HIGH (RTS off) until the receive FIFO reaches the Halt Level (TCR[3:0]). The
RTS# pin will return LOW after the RX FIFO is unloaded to the Resume Level (TCR[7:4]). Under these
conditions, the V2172 will continue to accept data if the remote UART continues to transmit data. It is the
responsibility of the user to ensure that the Halt Level is greater than the Resume Level. If interrupts are used,
it is recommended that Halt Level > RX Trigger Level > Resume Level. The Auto RTS function is initiated
when the RTS# output pin is asserted LOW (RTS On).
2.12
Auto CTS Flow Control
Automatic CTS flow control is used to prevent data overrun to the remote receiver FIFO. The CTS# input is
monitored to suspend/restart the local transmitter. The auto CTS flow control feature is selected to fit specific
application requirement (see Figure 12):
Enable auto CTS flow control using EFR bit-7.
If using the Auto CTS interrupt:
Enable CTS interrupt through IER bit-7 (after setting EFR bit-4). The UART issues an interrupt when the
CTS# pin is de-asserted (HIGH): ISR bit-5 will be set to 1, and UART will suspend transmission as soon as
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| XR20V2172L64-0A-EB | 功能描述:UART 接口集成電路 Supports V2172 64pin QFN, I2C Interface RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| XR20V2172L64-0B-EB | 功能描述:UART 接口集成電路 Supports V2172 64pin QFN, SPI Interface RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| XR-210 | 制造商:EXAR 制造商全稱:EXAR 功能描述:FSK MODULATOR / DEMODULATOR |
| XR-2100CJ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MODEM |
| XR-2100CP | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MODEM |
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