參數(shù)資料
型號： XR20V2172IL64-F
廠商： Exar Corporation
文件頁數(shù)： 1/51頁
文件大?。?/td> 0K
描述： IC UART/TXRX I2C/SPI RS232 64QFN
標準包裝： 260
特點： *
通道數(shù)： 2，DUART
FIFO's： 64 字節(jié)
規(guī)程： RS232
電源電壓： 2.97 V ~ 3.63 V
帶自動流量控制功能： 是
帶IrDA 編碼器/解碼器： 是
帶故障啟動位檢測功能： 是
帶調制解調器控制功能： 是
帶CMOS： 是
安裝類型： 表面貼裝
封裝/外殼： 64-VFQFN 裸露焊盤
供應商設備封裝： 64-QFN（9x9）
包裝： 托盤
Exar Corporation 48720 Kato Road, Fremont CA, 94538 (510) 668-7000 FAX (510) 668-7017 www.exar.com
XR20V2172
TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER
JUNE 2011
REV. 1.0.2
GENERAL DESCRIPTION
The XR20V21721 (V2172) is a high performance two
channel
universal
asynchronous
receiver
and
transmitter (UART) with 64 byte TX and RX FIFOs, a
selectable I2C/SPI slave interface and RS232
transceiver. The V2172 operates from 3.3 to 5.5 volts.
The enhanced features in the V2172 include a
programmable fractional baud rate generator, an 8X
and 4X sampling rate that allows for a maximum baud
rate of 1 Mbps at 3.3V. The standard features include
16 selectable TX and RX FIFO trigger levels,
automatic hardware (RTS/CTS) and software (Xon/
Xoff) flow control, and a complete modem interface.
Onboard registers provide the user with operational
status and data error flags. An internal loopback
capability allows system diagnostics. The V2172 is
available in the 64-pin QFN.
NOTE: 1 Covered by U.S. Patent #5,649,122
APPLICATIONS
Portable Appliances
Battery-Operated Devices
Cellular Data Devices
Factory Automation and Process Controls
FEATURES
Selectable I2C/SPI Interface
SPI clock frequency up to 18 MHz
Meets true EIA/TIA-232-F Standards from +3.3V to
+5.5V operation
Data rate up to 1 Mbps
45us sleep mode exit (charge pump to full power)
ESD protection for RS-232 I/O pins at
■ +/-15kV - Human Body Model
■ +/-15kV - IEC 61000-4-2, Air-Gap Discharge
■ +/- 8kV - IEC 61000-4-2, Contact Discharge
Full-featured UART
■ Fractional Baud Rate Generator
■ Transmit and Receive FIFOs of 64 bytes
■ 16 Selectable TX and RX FIFO Trigger Levels
■ Automatic Hardware (RTS/CTS) Flow Control
■ Automatic Software (Xon/Xoff) Flow Control
■ Halt and Resume Transmission Control
■ Automatic sleep mode
■ General Purpose I/Os
■ Full modem interface
64-QFN packages
FIGURE 1. XR20V2172 BLOCK DIAGRAM
U A R T
R S -232 T rans c eiv er
I2
C
/S
P
IIn
te
rf
a
ce
Cry s ta l
O s c /B u ffe r
XT
AL
1
XT
AL
2
BR G
64 B y te
TX & R X
FIFO
M odem
I/O s
UA
RT
R
e
gi
st
er
s
TX A
RX A
R T SA#
DT R A #
C T SA#
DS R A #
RIA #
CD A #
C harge P um p
TXD A
RT S A
DT RA
5K
RX DA
5K
CT S A
5K
DS RA
5K
RIA
5K
CDA
ACP
C2
+
C2
-
C1
+
C1
-
VC
C
VR EF+
VR EF-
GN
D
F
AST
R_
EN
C hannel B
CD B #
RIB #
DS R B #
CT S B #
C hannel A
DT RB #
RT S B #
TXB
RX B
C hannel B
T rans c eiv er
C h A T rans c eiv er
CD B
RIB
DS RB
CT S B
DT RB
RT S B
TX D B
RX DB
I2 C /S P I#
SD A
SC K
A0 /C SA #
A1 /S I
SO
IR Q #
R E SET #
RX B _ S E L
TX B
RX B
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