REV. 1.0.1 4.16 GPIO State Register (IOState) = Read/Write This" />
參數(shù)資料
型號： XR20V2170IL40-F
廠商： Exar Corporation
文件頁數(shù)： 26/49頁
文件大?。?/td> 0K
描述： IC UART/TXRX I2C/SPI RS232 40QFN
標(biāo)準(zhǔn)包裝： 490
特點： *
通道數(shù)： 1，UART
FIFO's： 64 字節(jié)
規(guī)程： RS232
電源電壓： 2.97 V ~ 3.63 V
帶自動流量控制功能： 是
帶故障啟動位檢測功能： 是
帶調(diào)制解調(diào)器控制功能： 是
帶CMOS： 是
安裝類型： 表面貼裝
封裝/外殼： 40-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 40-QFN 裸露焊盤（6x6）
包裝： 托盤
其它名稱： 1016-1478
XR20V2170IL40-F-ND
XR20V2170
32
I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER
REV. 1.0.1
4.16
GPIO State Register (IOState) = Read/Write
This register reports the state of all GPIO pins during a read and writes to any GPIO that is an output.
IOState[7:4]: Reserved
The values read from these bits should be ignored.
IOState[3:0]: GPIO[3:0] Status and Output control
If a GPIO is an input, then reading these bits will report the state of that pin. If a GPIO is an output, these bits
will control the state of that pin.
Logic 0 = set output pin LOW
Logic 1 = set output pin HIGH
4.17
GPIO Interrupt Enable Register (IOIntEna) - Read/Write
This register enables the interrupt for the GPIO pins.
IOIntEna[7:4]: Reserved
These bits should be set to ’0000’.
IOIntEna[3:0]: GPIO[3:0] Interrupt Enable
Logic 0 = a change in the input pin will not generate an interrupt
Logic 1 = a change in the input will generate an interrupt
4.18
GPIO Control Register (IOControl) - Read/Write
IOControl[7:4]: Reserved
IOControl[3]: UART Software Reset
Writing a logic 1 to this bit will reset the device. Once the device is reset, this bit will automatically be set to a
logic 0.
IOControl[2]: Reserved
IOControl[1]: Enable DTR#, DSR#, CD#, RI#
For normal operation, this bit should be set to a logic 1.
IOControl[0]: IO Latch
This bit enable/disable GPIO inputs latching.
Logic 0 = GPIO input values are not latched. A change in any GPIO input generates an interrupt. A read of
the IOState register clears the interrupt. If the input goes back to its initial logic state before the input register
is read, then the interrupt is cleared.
Logic 1 = GPIO input values are latched. A change in the GPIO input generates an interrupt and the input
logic value is loaded in the bit of the corresponding input state register (IOState). A read of the IOState
register clears the interrupt. If the input pin goes back to its initial logic state before the interrupt register is
read, then the interrupt is not cleared and the corresponding bit of the IOState register keeps the logic value
that generated the interrupt.
4.19
Extra Features Control Register (EFCR) - Read/Write
EFCR[7:3]: Reserved
These bits are reserved and should be left at "0000".
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