REV. 1.0.1 I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER IER[4]: Sleep Mode Enable (requires EFR bit-4 = 1)
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    • 參數(shù)資料
    型號： XR20V2170IL40-F
    廠商： Exar Corporation
    文件頁數(shù)： 16/49頁
    文件大?。?/td> 0K
    描述： IC UART/TXRX I2C/SPI RS232 40QFN
    標(biāo)準(zhǔn)包裝： 490
    特點(diǎn)： *
    通道數(shù)： 1，UART
    FIFO's： 64 字節(jié)
    規(guī)程： RS232
    電源電壓： 2.97 V ~ 3.63 V
    帶自動流量控制功能： 是
    帶故障啟動位檢測功能： 是
    帶調(diào)制解調(diào)器控制功能： 是
    帶CMOS： 是
    安裝類型： 表面貼裝
    封裝/外殼： 40-VFQFN 裸露焊盤
    供應(yīng)商設(shè)備封裝： 40-QFN 裸露焊盤（6x6）
    包裝： 托盤
    其它名稱： 1016-1478
    XR20V2170IL40-F-ND
    XR20V2170
    23
    REV. 1.0.1
    I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER
    IER[4]: Sleep Mode Enable (requires EFR bit-4 = 1)
    Logic 0 = Disable Sleep Mode (default).
    Logic 1 = Enable Sleep Mode. See Sleep Mode section for further details.
    IER[5]: Xoff Interrupt Enable (requires EFR bit-4=1)
    Logic 0 = Disable the software flow control, receive Xoff interrupt (default).
    Logic 1 = Enable the receive Xoff interrupt. See Software Flow Control section for details.
    IER[6]: RTS# Output Interrupt Enable (requires EFR bit-4=1)
    Logic 0 = Disable the RTS# interrupt (default).
    Logic 1 = Enable the RTS# interrupt. The UART issues an interrupt when the RTS# pin makes a transition
    from low to high.
    IER[7]: CTS# Input Interrupt Enable (requires EFR bit-4=1)
    Logic 0 = Disable the CTS# interrupt (default).
    Logic 1 = Enable the CTS# interrupt. The UART issues an interrupt when CTS# pin makes a transition from
    low to high.
    4.4
    Interrupt Status Register (ISR) - Read-Only
    The UART provides multiple levels of prioritized interrupts to minimize external software interaction. The
    Interrupt Status Register (ISR) provides the user with six interrupt status bits. Performing a read cycle on the
    ISR will give the user the current highest pending interrupt level to be serviced, others are queued up to be
    serviced next. No other interrupts are acknowledged until the pending interrupt is serviced. The Interrupt
    Source Table, Table 9, shows the data values (bit 0-5) for the interrupt priority levels and the interrupt sources
    associated with each of these interrupt levels.
    4.4.1
    Interrupt Generation:
    LSR is by any of the LSR bits 1, 2, 3, 4 and 7.
    RXRDY is by RX trigger level.
    RXRDY Time-out is by a 4-char plus 12 bits delay timer.
    TXRDY is by TX trigger level or TX FIFO empty.
    MSR is by any of the MSR bits 0, 1, 2 and 3.
    GPIO is when any of the GPIO inputs toggle.
    Receive Xoff/Special character is by detection of a Xoff or Special character.
    CTS# is when its transmitter toggles the input pin (from LOW to HIGH) during auto CTS flow control.
    RTS# is when its receiver toggles the output pin (from LOW to HIGH) during auto RTS flow control.
    4.4.2
    Interrupt Clearing:
    LSR interrupt is cleared by reading all characters with errors out of the RX FIFO.
    RXRDY interrupt is cleared by reading data until FIFO falls below the trigger level.
    RXRDY Time-out interrupt is cleared by reading RHR.
    TXRDY interrupt is cleared by a read to the ISR register or writing to THR.
    MSR interrupt is cleared by a read to the MSR register.
    GPIO interrupt is cleared by reading the IOState register.
    Xoff interrupt is cleared when Xon character(s) is received.
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