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參數(shù)資料
| 型號： | XR17V358IB-E8-EVB |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 11/68頁 |
| 文件大小： | 0K |
| 描述： | EVAL BOARD FOR XR17V358-E8 |
| 產(chǎn)品培訓(xùn)模塊： | PCIe UARTs UART Product Overview |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | 接口，UART |
| 嵌入式： | 否 |
| 已用 IC / 零件： | XR17V358 |
| 已供物品： | 板 |
| 相關(guān)產(chǎn)品： | 1016-1294-ND - IC UART PCIE OCTAL 176FPBGA |
| 其它名稱： | 1016-1296 |
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XR17V358
19
REV. 1.0.4
HIGH PERFORMANCE OCTAL PCI EXPRESS UART
1.4.1
The Global Interrupt Registers - INT0, INT1, INT2 and INT3
The XR17V358 has a 32-bit wide register [INT0, INT1, INT2 and INT3] to provide interrupt information and
supports two interrupt schemes. The first scheme is an 8-bit indicator representing all 8 channels with each bit
representing each channel from 0 to 7. This permits the interrupt service routine to quickly determine which
UART channels need servicing so that it can go to the appropriate UART channel interrupt service routines.
INT0 bit [0] represents the interrupt status for UART channel 0 when its transmitter, receiver, line status, or
modem port status requires service. Other bits in the INT0 register provide indication for the other channels
with bit [7] representing UART channel 7 respectively.
The second scheme provides detail about the source of the interrupts for each UART channel. All the interrupts
are encoded into a 3-bit code. This 3-bit code represents 7 interrupts corresponding to individual UART’s
transmitter, receiver, line status, modem port status. INT1, INT2 and INT3 registers provide the 24-bit interrupt
status for all 8 channels. bits [10:8] representing channel 0 and bits [31:29] representing channel 7
respectively. All 8 channel interrupts status are available with a single DWORD read operation. This feature
allows the host another method to quickly service the interrupts, thus reducing the service interval and host
bandwidth requirement.
Note that the interrupts reported in this register is specific to each UART channel. If there is a global interrupt
such as the wake-up interrupt, timer/counter interrupt or MPIO interrupt, they would be reported in the 3-bit
code for channel 0 in INT1.
GLOBAL INTERRUPT REGISTER (DWORD)
[default 0x00-00-00-00]
INT3 [31:24]
INT2 [23:16]
INT1 [15:8]
INT0 [7:0]
All bits start up zero. A special interrupt condition is generated by the V358 upon awakening from sleep after all
eight channels were put to sleep mode earlier. This wake-up interrupt is cleared by a read to the INT0 register.
Figure 4 shows the 4-byte interrupt register and its make up.
INT0 [7:0] Channel Interrupt Indicator
Ox098
MPIOINV[15:8]
Read/Write MPIO[15:8] input polarity select
Bits [15:8] = 0x00
Ox099
MPIOSEL[15:8]
Read/Write MPIO[15:8] select
Bits [15:8] = 0xFF
0x09A
MPIOOD[15:8]
Read/Write MPIO[15:8] open-drain output control
Bits [15:8] = 0x00
0x09B
Reserved
0x00
TABLE 6: DEVICE CONFIGURATION REGISTERS SHOWN IN DWORD ALIGNMENT
ADDRESS
REGISTER
BYTE 3 [31:24]
BYTE 2 [23:16]
BYTE 1 [15:8]
BYTE 0 [7:0]
0x0080
-0x0083
INTERRUPT (read-only)
INT3
INT2
INT1
INT0
0x0084-0x0087
TIMER (read/write)
TIMERMSB
TIMERLSB
Reserved
TIMERCNTL
0x0088-0x008B
ANCILLARY1 (read/write)
SLEEP
RESET
4XMODE
8XMODE
0x008C-0x008F
ANCILLARY2 (read-only)
MPIOINT[7:0]
REGB
DVID
DREV
0x0090-0x0093
MPIO1 (read/write)
MPIOSEL[7:0]
MPIOINV[7:0]
MPIO3T[7:0]
MPIOLVL[7:0]
0x0094-0x0097
MPIO2 (read/write)
MPIO3T[7:0]
MPIOLVL[15:8]
MPIOINT[15:8]
MPIOOD[7:0]
0x0098-0x009B
MPIO3 (read/write)
Reserved
MPIOOD[15:8]
MPIOSEL[15:8]
MPIOINV[15:8]
TABLE 5: DEVICE CONFIGURATION REGISTERS SHOWN IN BYTE ALIGNMENT
ADDRESS [A7:A0]
REGISTER
READ/WRITE COMMENT
RESET STATE
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