參數(shù)資料
型號: XR17V252IM-F
廠商: Exar Corporation
文件頁數(shù): 47/69頁
文件大?。?/td> 0K
描述: IC UART PCI BUS DUAL 100TQFP
標(biāo)準(zhǔn)包裝: 90
特點(diǎn): *
通道數(shù): 2,DUART
FIFO's: 64 字節(jié)
規(guī)程: RS485
電源電壓: 3.3V,5V
帶自動流量控制功能:
帶IrDA 編碼器/解碼器:
帶故障啟動位檢測功能:
帶調(diào)制解調(diào)器控制功能:
安裝類型: 表面貼裝
封裝/外殼: 100-TQFP
供應(yīng)商設(shè)備封裝: 100-TQFP(14x14)
包裝: 托盤
XR17V252
51
REV. 1.0.2
66 MHZ PCI BUS DUAL UART WITH POWER MANAGEMENT SUPPORT
MSR [2]: Receiver Disable
This bit can be used to disable the receiver by halting the Receive Shift Register (RSR). When this bit is set to
a logic 1, the receiver will operate in one of the following ways:
If a character is being received at the time of setting this bit, that character will be correctly received. No
more characters will be received.
If the receiver is idle at the time of setting this bit, no characters will be received.
The receiver can be enabled and will start receiving characters by resetting this bit to a logic 0. The receiver
will operate in one of the following ways:
If the receiver is idle (RX pin is HIGH) at the time of setting this bit, the next character will be received
normally. It is recommended that the receiver be idle when resetting this bit to a logic 0.
If the receiver is not idle (RX pin is toggling) at the time of setting this bit, the RX FIFO will be filled with
unknown data.
Any data that is in the RX FIFO can be read out at any time whether the receiver is disabled or not.
Logic 0 = Enable Receiver (default).
Logic 1 = Disable Receiver.
MSR [1:0]: Reserved
5.12
SCRATCH PAD REGISTER (SPR) - Read/Write
This is a 8-bit general purpose register for the user to store temporary data. The content of this register is
preserved during sleep mode but becomes 0xFF (default) after a reset or a power off-on cycle.
5.13
FEATURE CONTROL REGISTER (FCTR) - Read/Write
FCTR[7:6]: TX and RX FIFO Trigger Table Select
These 2 bits select the transmit and receive FIFO trigger level table A, B, C or D. When table A, B, or C is
selected the auto RTS flow control trigger level is set to "next FIFO trigger level" for compatibility to ST16C550
and ST16C650 series. RTS/DTR# triggers on the next level of the RX FIFO trigger level, in another word, one
FIFO level above and one FIFO level below. See Table 16 for complete selection with FCR bit [5:4] and FCTR
bits [7:6], i.e. if Table C is used on the receiver with RX FIFO trigger level set to 56 bytes, RTS/DTR# output will
de-assert at 60 and re-assert at 16.
FCTR[5]: Auto RS485 Enable
Auto RS485 half duplex control enable/disable.
Logic 0 = Standard ST16C550 mode. Transmitter generates an interrupt when transmit holding register
(THR) becomes empty. Transmit Shift Register (TSR) may still be shifting data bit out.
Logic 1 = Enable Auto RS485 half duplex direction control. RTS# output changes from HIGH to LOW when
finished sending the last stop bit of the last character out of the TSR register. It changes from LOW to HIGH
when a data byte is loaded into the THR or transmit FIFO. The change to HIGH occurs prior sending the
start-bit. It also changes the transmitter interrupt from transmit holding to transmit shift register (TSR) empty.
FCTR[4]: Infrared RX Input Logic Select
Logic 0 = Select RX input as active HIGH encoded IrDA data, normal (default).
Logic 1 = Select RX input as active LOW encoded IrDA data, inverted.
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