參數(shù)資料
型號(hào): XR16C2852
廠商: Exar Corporation
英文描述: 3.3V AND 5V DUART WITH 128-BYTE FIFO
中文描述: 3.3V和5V杜阿爾特128字節(jié)FIFO
文件頁數(shù): 9/42頁
文件大?。?/td> 574K
代理商: XR16C2852
XR16C2852
REV. 2.0.0
3.3V AND 5V DUART WITH 128-BYTE FIFO
á
9
Each UART also has their own prescaler along with
the BRG. The prescaler is controlled by a software bit
in the MCR register. The MCR register bit-7 sets the
prescaler to divide the input crystal or external clock
by 1 or 4. The clock output of the prescaler goes to
the BRG. The BRG further divides this clock by a pro-
grammable divisor between 1 and (2
16
-1) to obtain a
16X sampling rate clock of the serial data rate. The
sampling rate clock is used by the transmitter for data
bit shifting and
receiver for data sampling.
Programming the Baud Rate Generator Registers
DLM and DLL provides the capability of selecting the
operating data rate. Table 5 shows the standard data
rates available with a 14.7456 MHz crystal or external
clock at 16X sampling rate clock rate. When using a
non-standard data rate crystal or external clock, the
divisor value can be calculated for DLL/DLM with the
following equation.
F
IGURE
5. E
XTERNAL
C
LOCK
C
ONNECTION
FOR
E
XTENDED
D
ATA
R
ATE
2K
XTAL1
XTAL2
R1
VCC
External Clock
vcc
gnd
F
IGURE
6. B
AUD
R
ATE
G
ENERATOR
AND
P
RESCALER
XTAL1
XTAL2
Crystal
Osc/
Buffer
MCR Bit-7=0
(default)
MCR Bit-7=1
DLL and DLM
Registers
Prescaler
Divide by 1
Prescaler
Divide by 4
16X
Sampling
Rate Clock to
Transmitter
Baud Rate
Generator
Logic
divisor (decimal) = (XTAL1 clock frequency / prescaler) / (serial data rate x 16)
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