參數(shù)資料
型號: XR16C2852
廠商: Exar Corporation
英文描述: 3.3V AND 5V DUART WITH 128-BYTE FIFO
中文描述: 3.3V和5V杜阿爾特128字節(jié)FIFO
文件頁數(shù): 33/42頁
文件大?。?/td> 574K
代理商: XR16C2852
XR16C2852
REV. 2.0.0
3.3V AND 5V DUART WITH 128-BYTE FIFO
á
33
AC ELECTRICAL CHARACTERISTICS
TA=0
o
to
70
o
C (-40
o
to +85
o
C for industrial grade package), Vcc is 3.3 or 5.0V ±10%
S
YMBOL
P
ARAMETER
L
IMITS
3.3V
M
IN
M
AX
L
IMITS
5.0V
M
IN
M
AX
U
NIT
C
ONDITIONS
CLK
Clock Pulse Duration
50
17
ns
OSC
Oscillator Frequency
8
24
MHz
OSC
External Clock Frequency
33
50
MHz
T
AS
Address Setup Time
10
5
ns
T
AH
Address Hold Time
10
5
ns
T
CS
Chip Select Width
66
50
ns
T
RD
IOR# Strobe Width
35
25
ns
T
DY
Read Cycle Delay
40
30
ns
T
RDV
Data Access Time
50
35
ns
T
DD
Data Disable Time
0
35
0
25
ns
T
WR
IOW# Strobe Width
40
25
ns
T
DY
Write Cycle Delay
40
30
ns
T
DS
Data Setup Time
10
5
ns
T
DH
Data Hold Time
10
5
ns
T
WDO
Delay From IOW# To Output
50
40
ns
100 pF load
T
MOD
Delay To Set Interrupt From MODEM Input
40
35
ns
100 pF load
T
RSI
Delay To Reset Interrupt From IOR#
40
35
ns
100 pF load
T
SSI
Delay From Stop To Set Interrupt
1
1
Bclk
T
RRI
Delay From IOR# To Reset Interrupt
45
40
ns
100 pF load
T
SI
Delay From Stop To Interrupt
45
40
ns
T
INT
Delay From Initial INT Reset To Transmit Start
8
24
8
24
Bclk
T
WRI
Delay From IOW# To Reset Interrupt
45
40
ns
T
SSR
Delay From Stop To Set RXRDY#
1
1
Bclk
T
RR
Delay From IOR# To Reset RXRDY#
45
40
ns
T
WT
Delay From IOW# To Set TXRDY#
45
40
ns
T
SRT
Delay From Center of Start To Reset TXRDY#
8
8
Bclk
T
RST
Reset Pulse Width
40
40
ns
N
Baud Rate Divisor
1
2
16
-1
1
2
16
-1
-
Bclk
Baud Clock
16X of data rate
bps
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