參數(shù)資料
型號(hào): XR16C2852
廠商: Exar Corporation
英文描述: 3.3V AND 5V DUART WITH 128-BYTE FIFO
中文描述: 3.3V和5V杜阿爾特128字節(jié)FIFO
文件頁數(shù): 12/42頁
文件大小: 574K
代理商: XR16C2852
á
3.3V AND 5V DUART WITH 128-BYTE FIFO
XR16C2852
REV. 2.0.0
12
2.12.1 Receive Holding Register (RHR) - Read-
Only
The Receive Holding Register is an 8-bit register that
holds a receive data byte from the Receive Shift Reg-
ister. It provides the receive data interface to the host
processor. The RHR register is part of the receive
FIFO of 128 bytes by 11-bits wide, the 3 extra bits are
for the 3 error tags to be reported in LSR register.
When the FIFO is enabled by FCR bit-0, the RHR
contains the first data character received by the FIFO.
After the RHR is read, the next character byte is load-
ed into the RHR and the errors associated with the
current data byte are immediately updated in the LSR
bits 2-4.
N
OTE
:
Table-B selected as Trigger Table for Figure 10 (Table 10
on page 24).
F
IGURE
9. R
ECEIVER
O
PERATION
IN
NON
-FIFO M
ODE
Receive Data Shift
Register (RSR)
Receive
Data Byte
and Errors
RHR Interrupt (ISR bit-2)
Receive Data
Holding Register
(RHR)
RXFIFO1
16X Clock
Receive Data Characters
Data Bit
Validation
Error
Tags in
LSR bits
4:2
F
IGURE
10. R
ECEIVER
O
PERATION
IN
FIFO
AND
A
UTO
RTS F
LOW
C
ONTROL
M
ODE
Receive Data Shift
Register (RSR)
RXFIFO1
16X Clock
E
(
E
L
128 bytes by 11-bit
wide FIFO
Receive Data Characters
FIFO Trigger=16
Example:
- RX FIFO trigger level selected at 16 bytes
(See Note Below)
RTS# re-asserts when data falls below the flow
control trigger level to restart remote transmitter.
Enable by EFR bit-6=1, MCR bit-2.
Data fills to 24
Data falls to 8
Data Bit
Validation
Receive
Data FIFO
Receive
Data
Receive Data
Byte and Errors
RHR Interrupt (ISR bit-2) programmed for
desired FIFO trigger level.
FIFO is Enabled by FCR bit-0=1
RTS# de-asserts when data fills above the flow
control trigger level to suspend remote transmitter.
Enable by EFR bit-6=1, MCR bit-2.
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