參數(shù)資料
型號： XE8801AMI027LF
廠商： Semtech
文件頁數(shù)： 47/135頁
文件大?。?/td> 0K
描述： IC DAS 16BIT FLASH 8K MTP 44LQFP
標準包裝： 800
系列： XE880x
應(yīng)用： 感測機
核心處理器： Coolrisc816?
程序存儲器類型： 閃存（22 kB）
控制器系列： XE8000
RAM 容量： 512 x 8
接口： UART，USRT
輸入/輸出數(shù)： 24
電源電壓： 2.4 V ~ 5.5 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 44-VFQFN 裸露焊盤
包裝： 托盤
供應(yīng)商設(shè)備封裝： 44-MLPQ（7x7）
產(chǎn)品目錄頁面： 585 (CN2011-ZH PDF)
配用： XE8000MP-ND - PROG BOARD AND PROSTART2 CARD
Semtech 2005
www.semtech.com
3-2
XE8801A – SX8801R
3.1
CPU description
The CPU of the XE8000 series is a low power RISC core. It has 16 internal registers for efficient implementation of
the C compiler. Its instruction set is made up of 35 generic instructions, all coded on 22 bits, with 8 addressing
modes. All instructions are executed in one clock cycle, including conditional jumps and 8x8 multiplication. The
circuit therefore runs on 1 MIPS on a 1MHz clock.
The CPU hardware and software description is given in the document “Coolrisc816 Hardware and Software
Reference Manual”. A short summary is given in the following paragraphs.
The
good
code
efficiency
of
the
CPU
core
makes
it
possible
to
compute
a
polynomial
like
Y
B
X
Y
A
Z
+
+
=
1
0
1
0
)
(
in less than 300 clock cycles (software code generated by the XEMICS C-
compiler, all numbers are signed integers on 16 bits).
3.2
CPU internal registers
As shown in Figure 3-1, the CPU has 16 internal 8-bit registers. Some of these registers can be concatenated to a
16-bit word for use in some instructions. The function of these registers is defined in Table 3-1. The status register
stat (Table 3-2) is used to manage the different interrupt and event levels. An interrupt or an event can both be
used to wake up after a HALT instruction. The difference is that an interrupt jumps to a special interrupt function
whereas an event continues the software execution with the instruction following the HALT instruction.
The program counter (PC) is a 16 bit register that indicates the address of the instruction that has to be executed.
The stack (STn) is used to memorise the return address when executing subroutines or interrupt routines.
Instruction
memory
22bit
CPU
in
tern
al
r
egister
s
a
stat
iph
ipl
i3h
i3l
i2h
i2l
i1h
i1l
i0h
i0l
r3
r2
r1
r0
Data memory
da
ta
b
us
in
stru
ction
b
u
s
PC
ST
1
ST
2
ST
3
ST
4
program counter stack
Figure 3-1. CPU internal registers
Not
Recommended
for
New
Designs
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